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SNPS Synopsys

Synopsys, is the Silicon to Software™ partner for innovative companies developing the electronic products and software applications we rely on every day. As an S&P 500 company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and offers the industry's broadest portfolio of application security testing tools and services. Whether you're a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing more secure, high-quality code, Synopsys has the solutions needed to deliver innovative products.

Company profile

Ticker
SNPS
Exchange
CEO
Aart J. de Geus / Chi-Foon Chan
Employees
Incorporated
Location
Fiscal year end
SEC CIK
IRS number
561546236

SNPS stock data

(
)

Calendar

19 Feb 21
17 Apr 21
31 Oct 21
Quarter (USD)
Jan 21 Oct 20 Jul 20 Apr 20
Revenue
Cost of revenue
Operating income
Operating margin
Net income
Net profit margin
Cash on hand
Change in cash
Diluted EPS
Annual (USD)
Oct 20 Oct 19 Oct 18 Oct 17
Revenue
Cost of revenue
Operating income
Operating margin
Net income
Net profit margin
Cash on hand
Change in cash
Diluted EPS

Financial data from Synopsys earnings reports.

Cash burn rate (estimated) Burn method: Change in cash Burn method: Operating income/loss Burn method: FCF (opex + capex)
Last Q Avg 4Q Last Q Avg 4Q Last Q Avg 4Q
Cash on hand (at last report) 1.03B 1.03B 1.03B 1.03B 1.03B 1.03B
Cash burn (monthly) 70.86M (positive/no burn) (positive/no burn) (positive/no burn) (positive/no burn) (positive/no burn)
Cash used (since last report) 181.76M n/a n/a n/a n/a n/a
Cash remaining 843.64M n/a n/a n/a n/a n/a
Runway (months of cash) 11.9 n/a n/a n/a n/a n/a

Beta Read what these cash burn values mean

Date Owner Security Transaction Code Indirect 10b5-1 $Price #Shares $Value #Remaining
8 Apr 21 Sargent Jeannine P Common Stock Grant Aquire A No No 0 670 0 670
8 Apr 21 Chaffin Janice Common Stock Grant Aquire A No No 0 670 0 13,295
8 Apr 21 Nikias Chrysostomos L Common Stock Grant Aquire A No No 0 670 0 24,232
8 Apr 21 Schwarz John Common Stock Grant Aquire A No No 0 670 0 10,913
8 Apr 21 Vallee Roy Common Stock Grant Aquire A No No 0 670 0 50,239

Data for the last complete 13F reporting period. To see the most recent changes to ownership, click the ownership history button above.

88.3% owned by funds/institutions
13F holders
Current Prev Q Change
Total holders 686 633 +8.4%
Opened positions 114 70 +62.9%
Closed positions 61 49 +24.5%
Increased positions 244 229 +6.6%
Reduced positions 241 240 +0.4%
13F shares
Current Prev Q Change
Total value 34.87B 29.24B +19.3%
Total shares 134.48M 133.66M +0.6%
Total puts 467.5K 251.6K +85.8%
Total calls 688.2K 526.3K +30.8%
Total put/call ratio 0.7 0.5 +42.1%
Largest owners
Shares Value Change
Vanguard 17.02M $4.41B -2.3%
BLK Blackrock 12.78M $3.31B -0.1%
TROW T. Rowe Price 10.58M $2.74B -13.4%
JPM JPMorgan Chase & Co. 6.47M $1.68B +0.2%
STT State Street 6.34M $1.64B -2.6%
BEN Franklin Resources 3.37M $873M +7.6%
Pictet Asset Management 3.06M $792.62M +6.0%
Parnassus Investments 3.04M $789.08M +0.3%
IVZ Invesco 2.95M $763.62M -0.1%
Geode Capital Management 2.72M $702.72M +1.2%
Largest transactions
Shares Bought/sold Change
TROW T. Rowe Price 10.58M -1.63M -13.4%
Norges Bank 1.48M +1.48M NEW
WCM Investment Management 1.04M +1.02M +4782.4%
Carillon Tower Advisers 733.51K +687.11K +1480.8%
MKFCF Mackenzie Financial 312.4K -595.36K -65.6%
Ninety One UK 958.17K +519.16K +118.3%
Citadel Advisors 781.59K +502.85K +180.4%
Vanguard 17.02M -408.2K -2.3%
1832 Asset Management 428.6K -400.82K -48.3%
ARK Investment Management 1.02M +390.06K +61.8%
Content analysis
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Readability
H.S. freshman Avg
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Patents

GRANT
Utility
Method and apparatus for USB periodic scheduling optimization
6 Apr 21
A computerized system is disclosed.
GRANT
Utility
Generation of module and system-level waveform signatures to verify, regression test and debug SoC functionality
6 Apr 21
A method of detecting a fault in a circuit design undergoing emulation, includes in part, computing N signatures of a corresponding reference circuit design during each of the N cycles, computing N signatures of the circuit design undergoing emulation during each of the N cycles, comparing, for each of the N cycles, the signature of the reference circuit design to the signature of the circuit design undergoing emulation, and detecting whether a mismatch exists between the reference circuit design signature and the signature of the circuit design undergoing emulation during each of the N cycles.
GRANT
Utility
Identifying root cause of layout versus schematic errors
6 Apr 21
A layout versus schematic (LVS) tool identifies a detected mismatch between a first graph representing a circuit layout and a second graph representing a circuit schematic.
GRANT
Utility
Method and apparatus for memory noise-free wake-up protocol from power-down
6 Apr 21
A memory device having a wake-up protocol is disclosed.
GRANT
Utility
Clock generation and correction circuit
6 Apr 21
A clock generation and correction (CGC) circuit comprises a clock and data recovery (CDR) circuit, a start-of-frame (SOF) detector circuit, a counter, a digital logic circuit, a fractional-N phase locked loop (PLL), and an oscillator circuit.