ANNUAL REPORT ON FORM 10-K

FOR THE YEAR ENDED DECEMBER 31, 20162019

TABLE OF CONTENTS

PartPart I

This Annual Report on Form 10-K and the documents incorporated herein by reference contain forward-looking statements within the meaning of Section 27A of the Securities Act of 1933 and Section 21E of the Securities Exchange Act of 1934, which include, without limitation, statements about the market for our products, technology, our strategy, competition, expected financial performance and other aspects of our business identified in this Annual Report, as well as other reports that we file from time to time with the Securities and Exchange Commission. Any statements about our business, financial results, financial condition and operations contained in this Annual Report that are not statements of historical fact may be deemed to be forward- looking statements. Without limiting the foregoing, the words “believes,” “anticipates,” “expects,” “intends,” “plans,” “projects,” or similar expressions are intended to identify forward-looking statements. Our actual results could differ materially from those expressed or implied by these forward-looking statements as a result of various factors, including the risk factors described in Part I., Item 1A, “Risk Factors,” and elsewhere in this report. We undertake no obligation to update publicly any forward-looking statements for any reason, except as required by law, even as new information becomes available or other events occur in the future.

MoSysMoSys^®,1T-SRAM^®,1T-SRAM®,and Bandwidth Engine^®® and GigaChip® are registered trademarks of MoSys, Inc.  LineSpeed™ is a trademark and GigaChip^TM are trademarks of MoSys, Inc.

Item 1.  Business

Overview

MoSys, Inc., together with its subsidiaries (“MoSys,” the “Company,” “we,” “our” or “us”), is a fabless semiconductor company focused on the development and sale of integrated circuits, or ICs, for the high-speed cloud networking, communications, storagesecurity appliance, video, monitor and test, data center and computing markets. Our solutions deliver time-to-market, performance, signal integrity, power, area and economic benefits for system original equipment manufacturers, or OEMs. We have developed two ICOur primary product linesline is marketed under the Accelerator Engine name and comprises our Bandwidth Engine and LineSpeed product names. BandwidthProgrammable HyperSpeed Engine ICsIC products, which integrate our proprietary, 1T-SRAM high-density embedded memory with our integrated macro function technology and a highly efficienthighly-efficient serial interface protocol resulting in a monolithic memory IC solution optimized for memory bandwidth and transaction access performance.   Further performance benefits can be achieved to offload statistical, search or other custom functions using our optional integrated logic and processor elements.

As data rates and the bandwidth requirements and amount of high-speed processing per packet increase, in high-speed networking systems, critical memory access bottlenecks occur. Our BandwidthAccelerator Engine IC, with its combination of serial I/O, high-speed memory, offload functions and efficient, intelligent access, drastically increasesICs dramatically increase memory accesses per second, removing these bottlenecks. In addition, the serial interface and high memoryhigh-memory capacity reduce the board footprint, number of pins and complexity, while using less power. TheTo complement our Accelerator Engine ICs and utilize our technology we have recently introduced a new Software Accelerator product line that leverages our proprietary graphical memory engine technology to provide data classification capabilities.   These new software and IP products are hardware agnostic and operate with or without one of our Accelerator Engine IC products. We expect to begin licensing these products in the first half of 2020.

Our LineSpeed IC product line which we announced in March 2013, is comprised ofcomprises non-memory, high-speed serialization-deserialization interface, or SerDes I/O, physical layer, or PHY, devices that ensure signal integrity between interfaces which is commonly referred to as clock data recovery, or CDR, or retimer functionality, which perform multiplexing to transition from one speed to another, commonly referred to as Gearbox functionality. These PHY devices reside within optical modules and on networking equipment line cards designed for next-generation Ethernet and optical transport network applications.

We are currently supporting existing design win customers, primarily for Bandwidth Engine, and actively pursuing additional design wins for the use of our ICs in networking, communications and data center equipment. We have established initial pricing of our IC products ordered to date, but longer-term volume prices will be subject to negotiations with our customers and may vary substantially from these initial prices.

Prior to 2010, our primary business was the design, development, marketing, sale and support of differentiated intellectual property, or IP, including embedded memory and high-speed parallel and serial I/O used in advanced systems-on-chips, or SoCs. Currently, we are focused on developing differentiated IP-rich IC products and are dedicating all our research and development, marketing and sales budgets to these IC products. Royalty and other revenue generated from our existing IP agreements represented 45% of our total revenue in 2015 and 24% in 2016. We expect royalty and other revenue to continue to decline in 2017 both in absolute dollars and as a percentage of revenues.

Our future success and ability to achieve and maintain profitability are dependent on the marketing and sales of our IC products into networking, communications and other markets. Since the beginning of 2010, we have invested substantially all of our of our research and development resources toward development of our ICs, and, as of the end of 2012, had ceased our efforts to actively market our IP and establish license agreements for customers’ new SoC development projects.

Industry Background

The amount of data being transferredand the number of data consumers and devices is growing exponentially, driven primarily by networking, storagecommercial and computing systems is increasing rapidly, primarily driven by the growthconsumer cloud applications, video services, high speed mobile networks, Internet of the Internet and demand for real-time processing of bandwidth intensive applications, such as video-on-demand, Internet protocol TV, peer-to-peer and cloud computing, web2.0 applications, 4G/LTE wireless, voice-over-Internet protocol,Things, or IoT, and many others.other cloud applications. In order to meet these demands, the networknew cloud infrastructure, including the backbone, edge, access storagenetwork and data center infrastructurecenters, must scale in both speed and intelligence to handle real-time security, bandwidth allocation, and processing capability.service-level expectations. In addition, system designers faceworkloads or applications delivered at a massive scale from the challengecloud require flexible and efficient data transmission to optimize resources to enable these applications and lower the overall cost, size and power of increasing the throughput of all subsystems for a variety of applications, such as video games, medical record and imaging transfers, and file sharing.data center. These increased demands strain

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communication between onboard IC devices, limiting the data throughput in network switches and routers and the network backbone.

To meet these demands, carrier and enterprise networks are merging with the cloud and are undergoing significant changes and, most significantly, are migrating to packet-based Ethernet networks that enable higher throughput, lower cost and uniform technology across access, core and metro network infrastructure. These networks are now beinghave been designed to deliver voice and video andapplications over high-speed Internet accessservices on one converged, efficient and flexible network. These trends require networking systems, especially the high-speed switches, security appliances and routers that primarily comprise these networks, to comply with evolving market requirements and be capable of providing new services and better quality of service while supporting new protocols and standards. To support these trends,Traditional OEM network and telecommunications equipment manufacturers, such as Alcatel-Lucent (aNokia Corporation, and its subsidiary, of Nokia Corporation), Brocade Communications Systems, Inc.,Alcatel-Lucent, Cisco Systems, Inc., Tel. LM Ericsson, Fujitsu Ltd., Hitachi Ltd., Huawei Technologies, and Juniper Networks, Inc., Nokia Corporation,as well as new vendors and ZTE Corporation,cloud-service providers, who are delivering a new set of white-box solutions, must offer higher levels of packet forwarding rates, bandwidth density and be optimized to enable higher-density, lower powerlower-power data path connectivity in the next generations of their networking systems.

Networking communications, security, video and telecommunicationscomputing systems throughout the cloud network must operate at higher speed and performance levels, and so require new generations of packet processors and improved memory subsystems as well as new physical interface products, to enable system performance. These systems and their component line cards generally need to support aggregate rates of 100 gigabits per second, or Gbps, and above to meet the continued growth in network traffic. Cloud services have accelerated this transition with applications such as security. Data centers and access equipment that were previously aggregating slower traffic such at 1Gbpsrates of up to 10Gbps, and 40Gbps now are being designed to aggregate traffic at 10Gbps to 100Gbps, or more. The transition to 100 Gbpshigh-bandwidth networks has begun, and 100 Gbpsthe move to 100Gbps and higher rates at the edge (i.e., closer to the networks areand users generating data and voice traffic) is underway, and the increase in data rates for these networks is expected to continue to grow rapidly over the coming years.

SeveralThe systems that our customers build come in various sizes and utilize cards that contain several types of semiconductorssemiconductors. Line cards are included on eachfound in chassis-based systems that have slots and can contain up to 20 line cards. Our networking and communication system and certain other system customers typically use chassis-based systems. The alternative is systems that contain a single card; these systems are generally referred to as appliances or “pizza boxes.”  Cards that typically plug into a server or compute system are generally referred to as accelerator cards. We believe the wider use of these accelerator cards in systems throughout the network, especially at the edge, will expand the market opportunity for our products, as a number of these cards utilize field programmable gate array ICs, or FPGAs, as the packet processor. Our Accelerator Engines are ideally suited to support FPGAs performing these functions.  Each line card, including PHY,or accelerator card, includes one or more packet processors and multiple memory chips. PacketThese processors are complex ICs or IC chipsets that perform high speedhigh-speed data or packet processing for functions, such as traffic routing, shaping, metering, billing, statistics, detection, steering, security, video processing, monitoring and steering.workload acceleration. The line cards use various types of memory ICs to facilitate temporary packet storage and assist in the analysis and tracking of information embedded within each packetthe data flowing through the processors. After a packet enters the line card, through a PHY, a packet or data processor helps separate the packet into smaller pieces for rapid analysis. Typically,In a typical packet-based network for example, the data is broken up into the packet header, which contains vital information on packet destination and type, such as the Internet protocol address, and the payload, which contains the data being sent. Generally, the line card operations must occur at full data rates and typically require accessingfrequent access to the memory ICs many times. ICs.

Simultaneously, the packet’s payload, which may be substantially larger than the packet header, is also stored in memory ICs until processing is complete and the packet can re-combinebe re-combined and be sent to its next system destination. Within the line card, communication between the packet processor and memory ICs occurs through an interface consisting of combinations of physical pins on each type of chip. These pins are grouped together in a parallel or a serial architecture to form a pathway, called a bus, through which information is transferred from one IC to the next.

Today, the majority of physical buses that connect networking equipment and components use a parallel architecture to communicate between processors and memory ICs, which means information can travel only in one direction and in one instance at a time. As processing speeds increase, the number of pins required and the speed of the bus in a parallel architecture become a limitation on system performance and capability. In contrast, the number of connections is reduced substantially across fewer, higher-rate pins in a serial architecture, and data is transferred

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simultaneously in both directions. Data transfer rates with high-speed serial bus architectures and more advanced I/O protocols are limited by the capabilitiesdata access rates of the various ICs included on the line card, thus leading to bottlenecks when these ICs perform inadequately. In order to remove these bottlenecks and meet next-generation bandwidth requirements, the line card ICs mustneed to support higher access rates enabled by internal memory or high-speed serial bus architectures and these more advanced I/Ointerface protocols.

Most networking and communication systems sold and in operation today include line cards that process data at speeds ranging from 10 Gbps,10Gbps to 100 Gbps,400Gbps, and support many aggregated slower ports. To accommodate the substantial and growing increase in demand for networking communications and applications, networking systems manufacturers are developing and bringing to market next-generation systems that run at aggregate speeds of 100 to 400 Gbps or more with developments underwaynewer products scaling to scale totens of thousands of Gbps, or tens of terabits, per second. However, althoughApplications, such as security appliances, broadcast video and compute accelerators that were previously running at aggregate rates of 10Gbps or 40Gbps, are moving to higher aggregate rates in the 100s of Gbps.   Although processor performance in applications, such as computing and networking has continued to doubletraditionally doubled nearly every 18 months, or even sooner, the performance of external high-density memory technology has generally been able to double only once every 10 years. Existing memory IC solutions built for high capacity and based on parallel I/Ointerface architecture easily support speeds upstruggle to 40 Gbps, but are not optimal for meetingmeet the access rates required to meet speeds of 100 Gbps100Gbps and beyond due to system-level limitations for pin counts, power and performance. To compensate for slow external memory access, developers must either integrate larger amounts of on-chip memory and/or utilize complex system alternatives to try to work around the access-rate limitations of these memories. The additional memory and circuitry adds to IC power, size and cost and may not be feasible depending on the economics and technology used to implement the data processor. These networking and communications systems are generally comprised ofcomprise a chassis populated by four4 to 16 line cards. Often, these systems are shipped to customers with only a portion of the line card slots populated, and the customer will add additional line cards subsequently to increase system performance, capacity and capacity.features.

Each line card requires a significant amount of memory to support its processing capabilities. Traditional external memory IC solutions currently used on line cards include both dynamic random access memory, or DRAM, and static random access memory, or SRAM. Line cards in networking systems use both specialized, high-performance DRAM ICs, such as reduced-latency DRAM, or RLDRAM, low-latency DRAM, or LLDRAM, and commodity DRAM, such as double data rate, or DDR ICs.  In addition,The latest DDR memory is high-bandwidth memory, or HBM, which provides high bandwidth, but has fundamentally slow access time.  For very high access, networking systems use higher-performance SRAM, ICswhich may be integrated into the data processing IC itself depending on size, power and economics or use traditional external SRAM IC, such as quad data rate, or QDR SRAM. These memories are very fast, but are much smaller, cost more and burn more power than traditional DRAM. Substantially all of these traditional memory IC solutions use parallel interfaces, which are slower than serial interfaces, sointerfaces. For data processing solutions, which are unable to integrate large amounts of SRAM, such as field-programmable gate arrays (FPGA), we believe theythe traditional external SRAMs or RLDRAMs will be increasingly challenged to meet the performance, pin count, area and power requirements as networking systems and other new security, video, and compute systems expand beyond 100 Gbps.100Gbps. The result is a gap between processor and memory performance. To meet the higher performance requirements being demanded by the industry, while using current components and architectural approaches, system designers must add more discrete memory ICs to the line cards and/or add more embedded memory on the packet processor. This resultsNew processor and custom data processing engine ICs are being developed that integrate more SRAM to help offset the bottlenecks, but the cost to develop these custom ICs is high and there is a trade-off in highercost, power and size.  FPGAs offer flexibility, lower development cost and power consumption,time to market but are limited in the useamount of more space oninternal circuitry and the line cards and additional communication interference between the ICs, which in turn results in additional bandwidth limitation problems.amount of integrated SRAM memory. We believe our BandwidthAccelerator Engine family of products is well suited to address thesememory access bottleneck challenges and replace theseprovide significant performance, size, pin count and power advantages compared to traditional external memory solutions.solutions, primarily for FPGA-based systems.

In addition, each line card requires PHY productsorder to provide interoperabilityimprove performance and signal integrity functions. As network speeds increase beyond 100Gbps,resolve memory bottlenecks, in recent years, the serial data rates are transitioning from 10Gbpstrend has been to 25Gbps.have algorithms on the memory device perform computations in order to reduce processing time and power consumption. This means thattrend is sometimes called in-memory compute or processor-in-memory. In order to make a flexible solution, the signal integrity challenges (maintainingin-memory compute can be accomplished with arrays of reduced instruction set computer, or RISC, cores on the quality ofmemory device. Further performance gains can be accomplished with application-specific enhancements to the electrical signals) of moving these high speed signals around within line cards, or between line cards and systems using fiber optic or copper cable, increase as data rates increase. These networking systems often use copper or optical modules to modify signals for transmission over longer distances ranging from tens of meters to thousands of kilometers. Optical modules convert electrical signals to optical signals for transportation over longer distances from one system to another system. Because of the challenges arising from the increase in network speeds, new 100Gbps standards have emerged that specify a CDR or retimed interface on optical modules, which was not the case at 10Gbps based interfaces. Each 100Gbps module and above using 25Gbps per lane will require a CDR/retimer function inside the module to meet these requirements. In addition, the systems themselves also require additional support to move signals between the module and the system, and these challenges become more acute as the distance increases. Our LineSpeed products address these new line card and optical module challenges by providing unique signal integrity and feature sets that align with the industry standards, as well as provide backward compatibility for the previous data rates. We believe our LineSpeed PHY products are well suited ensure the quality of signals and/or increase the transmission distance for both short reach (e.g., between ICs on a line card) or long-reach (e.g., between line cards or systems).memory device’s instruction set architecture.

We have developed our Bandwidth Engine and LineSpeed families of ICs to synergistically address the need for high-speed data access and throughput currently confronting networking system designers. We expect our IC products to meet the increasing demands placed on conventional memory technology used on the line cards in high-bandwidth networkinghigh-speed systems. We believe that our products and

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technology are well positioned as replacements for existing IC solutions in order to meetsupport the needs of the next-generation networking systems that will require a largegrowing number of packet lookups and to support aggregatedFPGA-based data processing applications with aggregate rates greater than 100 Gbps.100Gbps that require high bandwidth and high access rate to memory.

Our Approach

Our historical business was focused on the licensing of our proprietary 1T- SRAM and SerDes I/O technologies. We have leveraged our proprietary IP to design our Bandwidth EngineIC products and LineSpeed IC product families

related acceleration IP to help networking OEMs in our target markets to address the growing bottlenecks in system performance. We have incorporated critical features into our product families to accomplish this objective.

On-Chip Functionality

One significant performance bottleneck in any network line card is the need to transfer data between discrete ICs. Many of these data-transfer operations are iterative in nature, requiring subsequent, back-to-back accesses of the memory IC by the processor IC. Our Bandwidth Engine ICs include an arithmetic logic unit, or ALU, which enables the Bandwidth Engine IC to perform mathematical operations on data. Moving certain processing functions from the processor IC to the Bandwidth Engine IC through the use of this embedded ALU, reduces the number of I/O transactions and frees the processor IC to perform other important networking or micro-processing functions.

High-Performance Interface

High-speed, efficient interface I/Osinterfaces are critical building blocks to meet high data transfer rate requirements for communication between ICs on network line cards. We believe that current networking system requirements necessitate an industry transition from parallel to serial I/O. As a result, semiconductorSemiconductor companies are increasingly turning to serial I/Ointerface architectures to achieve needed system performance. For example, high-performance ICs that are sold into wide markets, such as field programmable gate arrays, or FPGAs, and network processing units, NPUs, are using serial I/Os to ensure they can compete with custom designed application specific ICs, or ASICs, by matching their performance. Using serial I/O,interfaces, IC developers also are able to reduce pin countthe number of pins (the wired electrical pins that connect an IC to the network line card on which it is mounted) on the IC. With reducing geometries, the size of most high-performance ICs is dictated by the number of pins required, rather than the amount of logic and memory embedded in the chip. As a result, using a serial I/Ointerface facilitates cost reduction and reduced system power consumption, while improving the performance of both the IC itself and the overall system. While SerDes I/Osserial interfaces provide significantly enhanced performance over parallel I/Os,interfaces, SerDes I/Osinterfaces traditionally have had higher power consumption, which is a challenge for IC designers. Our SerDes I/Os,interfaces, however, are tuned for low power consumptionoptimized to meet our customers’ stringent powersignal integrity, low-power consumption and latency requirements.

We make our I/Ointerface technologies compliant with industry standards so that they can interoperate with interfaces on existing ICs. In addition, we make them programmable to support multiple data rates, which allows for greater flexibility for the system designer, while lowering their development and validation costs. Interoperability reduces development time, thereby reducing the overall time to market of our customers’ systems.

Analog Design Capabilities

We have invested in personnel needed to define, design and market high- performance analog IC products. We have built a team of experienced engineers who combine industry expertise with advanced semiconductor design expertise to meet customer requirements and develop new products to bring to market. We initially developed our team of analog engineers to develop the SerDes I/O used in our Bandwidth Engine families of products. We leveraged the capabilities of this team to produce our LineSpeed IC products, which are primarily comprised of analog circuitry.

GigaChip Interface Protocol

In addition to the physical characteristics of the serial I/O,interface, the protocol used to transmit data is also an important element that impacts speed and performance. To address this and complement our BandwidthAccelerator Engine devices, we have developed the GigaChip Interface,®, or GCI, which is an open-interface transport protocol optimized for efficient chip-to-chip communications. The GCI electrical interface is compatible with the current industry standard (Common Electrical Interface, release #11, or CEI-11G-SRstandards, including 10G and XFI)25G IEEE and OIF interface standards, to simplify electrical interoperability between devices. GCI can enable highly efficient serial chip-to-chip communications, and its transport efficiency averages 90% for the data transfers it handles. GCI is included in our Bandwidth Engine ICs and is offered to customers and prospective partners on terms intended to encourage widespread adoption.

High-Performance and High-Density Memory Architecture

The high-densityhigh density of our proprietary 1T-SRAM technologiestechnology stems from the use of a single-transistor, or 1T, which is similar to DRAM, with a storage cell for each bit of information. Embedded memory utilizing our 1T-SRAM technologies is typically two to three times denser than the six-transistor storage cells used by traditional SRAM, or 6T-

SRAM.6T-SRAM. Embedded memory utilizing our 1T-SRAM technologies typically provides speeds essentially equal to or greater than the speeds of traditional SRAM and DRAM, particularly for larger memory sizes. Our 1T-SRAM memory designs can sustain random access cycle times of less than three nanoseconds, significantly faster than embedded 6T-SRAMDRAM technology. Embedded memory utilizing our 1T-SRAM technologies can consume as little as one-half the active power and generate less heat than traditional SRAM when operating at the same speed. This reducesThe 1T-SRAM allows us to integrate more high-performance memory using less expensive processing technology, reduce system level heat dissipation and enablesenable reliable operation using lower-cost packaging.

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Embedded In-Memory Functions

We have combined our high-speed memory architecture with intelligence to define an embedded memory that can execute embedded functions and algorithms internally, or “in-memory,” to allow software and hardware designers acceleration options to improve the performance of their applications.

The in-memory functions executed within the memory architecture in our Accelerator Engine products result in application-performance increases by reducing the number of external memory and computational operations needed to accomplish the same functions using traditional memories.  Also, by executing in-memory, the resources of the packet processor and other ICs on the customer’s board are available to perform other functions.

Our Accelerator Engine ICs include an arithmetic logic unit, or ALU, which enables the performance of mathematical operations on data. Moving certain processing functions from the host data processor IC to the Accelerator Engine IC through the use of this embedded ALU, reduces the number of processing transactions and frees the host data processor IC to perform other important networking or micro-processing functions.

Our Programmable HyperSpeed Engine IC takes this concept one step further by incorporating integrated RISC processors optimized for processing data structures and graphs.  Our Programmable HyperSpeed Engine IC integrates RISC cores optimized for operating data stored in the memory block.  The integration of the cores with memory allows system algorithms or functions to be offloaded to the device and reduces overall system-task latency and increases throughput.  The processors can be programmed by the user to offload and accelerate standard and/or customized functions from the main processor thereby reducing memory transactions and data path complexity to provide improved performance and lower cost packaging.system latency.  New algorithms or functions can be added to or modified in the Programmable HyperSpeed Engine IC in software.

Our Strategy

Our primary business objective is to be ana profitable IP-rich fabless semiconductor company offering ICs and related software and IP that deliver unparalleled memory bandwidth and access rate performance for packethigh-performance data processing and improved signal integrity performance forin cloud networking, security appliances, video, test and monitoring, and data center systems. The key components of the expansion of our strategic plan to become an IC supplier include the following strategies:

Target Large and Growing Markets

Our initial strategy isPrior to target2019, our primary focus was the multi-billion dollar networking, telecommunications, security appliance and data center OEM equipment markets, and we haveas our products were developed products to support the growth in 100 Gbps100Gbps and higher networking speeds. During 2019, we expanded our market focus to new markets, including video, test and measurement and computing markets. We are currently supporting approximately 25 existingnumerous customers across these markets, with whom we have achieved over 85 design wins, which reflects broadening acceptance of our products.wins. We define a design win as the point at whicha commitment from a customer has made a commitment to build a board against the fixed schematic for his system, and this board will utilize one of our IC products.products in its system. We continue to actively pursue additional design wins for the use of our ICs in our target markets. We believe our design wins represent the potential for significant future revenues. With limited historyrevenue growth. However, there is no assurance that these customer designs will be shipped in large volume by our customers to date, however, we cannot estimatetheir customers, how much revenue each design win is likely to generate, or how much revenue all of these (and future design wins) are likely to generate. For example, our first design wins from 2012 and 2013 are starting to ramp into production, and, while we cannot predict how steep these ramps might be, we expect our revenues from them to grow in successive periods over the next few years. There is no assurance that these customer designs will be shipped in large volume by our customers to their customers, however.

Leverage Technologies to Create New Products

Our strategy is to combine our proprietary IP and design and applications expertise to address the needs of several upcoming generations of advanced networking systems. We believe an IC combining our 1T-SRAM and serial I/O with logic, such as in an ALU, and other functions can provide a system-level solution and significantly improve overall system performance at lower cost while using less power. We also seek to leverage our high-speed serial I/O to create non-memory denominated ICs, such as our LineSpeed products. Our initial LineSpeed products targeted the line card and the same customers as our Bandwidth Engine products. This has given us the opportunity to provide both memory and PHY solutions during the sale process. In 2013, we introduced our first LineSpeed products to address the requirements new industry standards were placing on optical modules, as well as line cards.

Expand Adoption of the GigaChip Interface Protocol

We have provided our GCI interface protocol as an open industry standard that may be designed into other ICs in the system, as we believe this will further enable serial communication on network line cards and encourage adoption of our Bandwidth Engine IC products. A number of IC providers and partners have publicly announced their support of GCI and Bandwidth Engine, including the largest FPGA providers, Altera Corporation (a subsidiary of Intel Corporation), Xilinx, Inc., and EZchip Semiconductor Ltd. (a subsidiary of Mellanox Technologies Ltd.), with whom we work closely to support common customers. In addition, multiple networking systems companies, including actual and prospective customers, have adopted GCI.

Build Long-Term Relationships with FPGA Vendors and Suppliers of Packet ProcessorsData Processing Solutions

We believe that having long-term relationships with packet processorFPGA providers is critical to our success, as such relationships may enable us to reduce our time-to-market, provide us with a competitive advantage and expand our target markets. A key consideration of network system designers is to demonstrate interoperability between our Bandwidth Engine IC products and the packet processorsprocessor ICs  utilized in their systems. To obtain design wins, for our Bandwidth Engine IC, we must demonstrate this interoperability, and also show that our IC works optimally with the packet

processor to achieve the performance requirements. In addition, our current strategy requires packet processor suppliers to adopt our GCI interface. To that end, we have been working closely with FPGA ASIC and NPUapplication specific standard product providers to enable interoperability between our BandwidthAccelerator Engine IC products and their high-performance products. To facilitate the acceptance of our BandwidthAccelerator Engine ICs, we have made available development and characterization kits for system designers to evaluate and develop code for next-generation networking systems. Our characterization kits are fully-functional hardware platforms that allow FPGA and ASIC providers, and their customers, to demonstrate interoperability of the BandwidthAccelerator Engine IC with the ASIC or FPGA the designers use within their networking systems.

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Our recent announcementIC Products

Accelerator Engines

Our Accelerator Engine IC products, include the Bandwidth Engine, which is targeted for high-performance applications where throughput is critical, and the Programmable HyperSpeed Engine, which combines the features of the third-generation Bandwidth Engine Z30 device, designed for interoperability with 32 RISC processors to allow user-defined functions or algorithms to be embedded in the EZ-chip NPS-400, is an example and direct result of this strategy.

Our ProductsProgrammable HyperSpeed Engine.

Bandwidth Engine

The Bandwidth Engine is a memory-dominated IC that has been designed to be a high-performance companion IC to packet processors. While the Bandwidth Engine primarily functions as a memory device with a high-performance and high-efficiency interface, it also can accelerate certain processing operations by serving as a co-processor element. Our Bandwidth Engine ICs combine: (1) our proprietary high-density, high-speed, low latency embedded memory, (2) our high-speed serial interface technology, or SerDes, (3) an open-standard interface protocol and (4) intelligent access technology. We believe an IC combining our 1T-SRAM memory and serial I/Ointerface with logic and other intelligence functions provides a system-level solution and significantly improves overall system performance at lower cost, size and power consumption. Our Bandwidth Engine ICs can provide up to and over 4.56.5 billion memory accesses per second externally and 12 billion memory accesses per second internally, which we believe is more than twicethree times the performance of current memory-based solutions. They also can enable system designers to significantly narrow the gap between processor and memory IC performance. CustomersOur customers that design Bandwidth Engine ICs onto the line cards in their networking systems will re-architect their systems at the line-card level and use our product to replace traditional memory solutions. When compared with existing commercially available solutions, our Bandwidth Engine ICs may:

Our first generation Bandwidth Engine 2 IC products contain 576 megabytes,megabits, or MB,Mb, of memory and use a serial I/OSerDes interface with up to 16 lanes operating at up to 10.3 Gbps12.5Gbps per lane. Variations of this IC can have up to two interface ports, with up to eight serial receiver and eight serial transmitter lanes per port for a total of 16 lanes of 10.3 Gbps SerDes interface. These ICs include an ALU, which can perform read-modify-write operations. We have been shipping our initial Bandwidth Engine products since 2012.

Our second generation Bandwidth Engine IC products contain 576 MB of memory and use serial I/O with up to 16 lanes operating at up to 15 Gbps per lane. In addition to a speed improvement of up to 50%, the architecture will enable several family member parts with added specialized features. To date, we have announced three unique devices in this product family:

We have been shipping our Bandwidth Engine 2 IC products since 2013.

We continue to win new designs for this device family, and expect these products to be our primary revenue source for the foreseeable future.

Our third generation Bandwidth Engine 3 IC products contain 1152 MB1152Mb of memory and use serial I/Oa SerDes interface with up to 16 lanes operating at up to 30 Gbps25Gbps per lane. Our Bandwidth Engine 3 targetsICs target support for packet-processing applications with up to five billion memory single word accesses per second, as well as burst mode to enable full duplex buffering up to 400Gbps400 Gbps for ingress, egress and oversubscription applications. To date, we have announced three unique devices in this product family:

We commenced sampling of these products in the first quarter of 2016.

The devices provide benefits of size, power, pin count and cost savings to our customers. We do not anticipate significant revenues from these products until 2018 or later.

Programmable SearchHyperSpeed Engine

We brought ourOur Programmable SearchHyperSpeed Engine or PSE, IC products to market in early 2016 to further leverage our proven serial interface technology and high-density integrated memory with the processor engine architecture to enable high-speed customizable search, security, and data analysis functions for networking, security, and data center applications. Our PSEapplications, as well as new markets such as video and compute acceleration. The product architecture features 32 search-optimized processor engines, data flow schedulers, and over a terabit of internal access bandwidth. The device leverages our GCI interface technology and high-density integrated memory (1152 Mb(1152Mb of 1T-SRAM®1T-SRAM embedded memory). The PSE device’s 32 processor elements have direct access to integrated table memory through an internal interconnect and scheduler architecture.

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LineSpeed Flex PHYs

Our first generation LineSpeed products consist of single-chip PHY ICs, including a 100G multi-mode gearbox and a 100G quad retimer. These devices are designed to support 10, 40 and 100Gbps standards for high-density line cards or modules for next generation ethernet and optical transport network applications. These devices are capable of supporting both short and long reach connections across different specifications. We have developed these PHY ICs to provide the CDR function and to provide signal conversion from lower rates to higher rates both on the line card and within the optical module. We have defined performance and form factor (sizes) for specific devices for optimization of features and performance to solve space challenges both on the line card and in the optical module. We introduced and began sampling these devices in 2013.

Our second generation of LineSpeed products consists of our 100G low power retimer, which is optimized for ultra low power consumption, integrated test features and small size. The low-power retimer is primarily targeting opportunities in 100G CFP2, CFP4 and QSFP28 optical modules and active copper cables. We introduced and began sampling this product in 2014.

Our third generation of LineSpeed products, the Flex family of 100G PHYs, is designed to support the latest industry standards and includes gearbox, Multi-Link Gearbox, or MLG, and high density CDR/retimer devices designed to enable existing and next generation Ethernet and OTN line card applications to support the latest high-density electrical and optical interfaces. To date, we have announced four unique devices in this product family:

suppliers they can choose from. We must provide differentiated features with a reasonable IC power budget, while offering competitive pricing.  To date, we have had limited success selling and marketing these products.

Manufacturing

We depend on third-party vendors to manufacture, package, assemble and test our IC products, as we do not own or operate a semiconductor fabrication, packaging or production testing facility for boards and system assembly.facility. By outsourcing manufacturing, we are able tocan avoid the high cost associated with owning and operating our own facilities, allowing us to focus our efforts on the design and marketing of our products.

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We perform an ongoing review of our product manufacturing and testing processes. Our IC products are subjected to extensive testing to assess whether their performance meets design specifications. Our test vendors provide us with immediate test data and the ability to generate characterization reports that are made available to our customers. We have achieved ISO 9001:20082015 certification, and all of our significant manufacturing vendors have also achieved ISO 9001 certification.

Employees

As of December 31, 2016,2019, we had 6323 employees all of whom are located in the United States, consisting of 3614 in research and development 7 in sales and marketing, 11 in manufacturing operations and 9 in financesales, marketing and administration. By location, we had 61 employees in the United Statesgeneral and 2 sales and marketing employees in Asia.administrative functions.

Available Information

We were founded in 1991 and reincorporated in Delaware in September 2000. Our website address is www.mosys.com. The information in our website is not incorporated by reference into this report. Through a link on the Investor section of our website, we make available our annual reports on Form 10-K, quarterly reports on Form 10-Q, current reports on Form 8-K, and any amendments to those reports filed or furnished pursuant to Section 13(a) or 15(d) of the Securities Exchange Act of 1934, as soon as reasonably practicable after they are filed with, or furnished to, the Securities and Exchange Commission, or SEC. You can also read and obtain copies of any materials we file withsubmitted electronically by us to the SEC at the SEC’s Public Reference Room at 450 Fifth Street, NW, Washington, DC 20549. You can obtain additional information about the operation of the Public Reference Room by calling the SEC at 1.800.SEC.0330. In addition, the SEC maintains aon its website (www.sec.gov) that, which contains reports, proxy and information statements, and other information regarding issuers that file electronically with the SEC, including us.

Item 1A.  Risk Factors

If any of theThe following risks actually occur,could materially and adversely affect our business, financial condition, cash flows, and results of operations, and the trading price of our common stock could decline. These risk factors do not identify all risks that we face. Our operations could also be affected by factors that are not presently known to us or that we currently consider to be immaterial to our operations. Due to risks and uncertainties, known and unknown, our past financial condition could suffer significantly.results may not be a reliable indicator of future performance, and historical trends should not be used to anticipate results or trends in future periods. Refer also to the other information set forth in this Annual Report on Form 10-K, including in Part II, Item 7, “Management’s Discussion and Analysis of Financial Condition and Results of Operations” as well as our Consolidated Financial Statements and the related notes in Part II, Item 15.

We have a history of losses and we will need to raise additional capital in the future and our inability to do so may adversely impact our ability to continue as a going concern.future.

Our consolidated financial statements have been prepared on a going concern basis that assumes we will be able to realize our assets and discharge our liabilities in the normal course of business for the foreseeable future. We recorded an operatinga net loss of approximately $31$2.6 million for the year ended December 31, 20162019, and we ended the period with an accumulated deficit of approximately $214$238 million. In addition, weWe recorded operating lossesa net loss of approximately $31 million and $33$11.4 million for the yearsyear ended December 31, 20152018, and 2014, respectively. ended the period with an accumulated deficit of approximately $236 million. These and prior-year losses have resulted in significant negative cash flows for more almost a decade and have required us to raise substantial amounts of additional capital during this period. We expect to continue to incur operating losses for the foreseeable future as we secure customers forTo remain competitive and continue to invest in the commercialization of our IC products. Due to the strong commitment of our resources to research and development and expansion ofexpand our product offerings to customers, we will need to increase revenues substantially beyond levels that we have attained in the past in order to generate sustainable operating profit and sufficient cash flows to continue doing business without raising additional capital from time to time. Given our history of fluctuating revenues and operating losses, the expected reduction in royalty and licensing revenues andthe challenges we face in securing customers for our IC products, we cannot be certain that we will be able to achieve and maintain profitability on either a quarterly or annual basis in the future. The possibility that we will not be able to meet our obligations as and when they become due over the next twelve months raises substantial doubt about our ability to

continue asAs a going concern.

Accordingly, we have been pursuing, and will continue to pursue, the implementation of certain cost reduction strategies. Additionally, we are seeking additional financing and evaluating financing alternatives in order to meet our cash requirements for the next 12 months. We may not be able to obtain additional financing, as needed, on acceptable terms, or at all, which may require us to further reduce our operating costs and other expenditures, including additional reductions of personnel and capital expenditures. Alternatively, or in addition to such potential measures, we may elect to implement other cost reduction actions as we may determine are necessary and in our best interests, including the possible sale or cessation of certain of our business segments. Any such actions undertaken might limit our opportunities to realize plans for revenue growth, and we might not be able to reduce our costs in amounts sufficient to achieve break-even or profitable operations. If we issue additional equity or convertible debt securities to raise funds, the ownership percentage of our existing stockholders would be reduced and they may experience significant dilution. New investors may demand rights, preferences or privileges senior to those of existing holders of our common stock. If we are not successful in these actions, we may be forced to cease operations. See Management’s Discussion and Analysis of Financial Condition, “Results of Operations, Liquidity and Capital Resources, and Going Concern-Working Capital.”

Our auditor has expressed substantial doubt about our ability to continue as a going concern and, absent additional financing, we may be unable to remain a going concern.

In light of our recurring losses, accumulated deficit and negative cash flow, as described in the notes to our consolidated financial statements, the report of our independent registered public accounting firm on our financial statements for the year ended December 31, 2016 contains an explanatory paragraph raising substantial doubt about our ability to continue as a going concern.  Our consolidated financial statements do not include any adjustments that may be necessary in the event we are unable to continue as a going concern.  If we do not raise enough additional capital sufficient to allow for the removal of this going concern uncertainty,result, we will need to significantly modify our operational plans forraise additional capital in the future, which may or may not be available to us to continue as a going concern.

at all or only on unfavorable terms.

Our failure to raise additional capital or generate the significant capital necessary to expand our operations and invest in the new products could reduce our ability to compete and could harm our business.

We intend to continue spending substantial amounts to grow our business. In March 2016, we issued $8 million aggregate principal amountDespite the successful completion of 10% Subordinateour public offering and repayment of a portion of and extension of the repayment date for  our Senior Secured Convertible Notes due August 15,in October 2018, (the Notes). The Note principal is convertible into our common stock, as well as the interest on the Notes, as we have the option of paying the interest in-kind by converting such interest into additional note principal.  In addition, the Notes also include limited anti-dilution protection, such that the conversion price will be reset to a lower conversion price in some situations.  As a result, our stockholders may experience significant dilution of these Notes and any additional paid-in-kind principal are converted into our common stock and the conversion price is reset.  We will still might need to obtain additional financing to pursue our business strategy, develop new products, respond to competition and market opportunities and acquire complementary businesses or technologies.technologies, in addition to repaying these notes. There can be no assurance that such additional capital, whether in the form of debt or equity financing, will be sufficient or available and, if available, that such capital will be offered on terms and conditions acceptable to us.  We are exploring various alternatives, and expect to implement cost reductions to successfully sustain the business.  If we are unsuccessful in these efforts, we will need to implement significant cost reduction strategies that could affect our near- and long-term business plan.  These efforts may include, but are not limited to reducing headcount and curtailing business activities, especially around new product development.

If we were to raise additional capital through sales of our equity securities, our stockholders would suffer dilution of their equity ownership.ownership, as exemplified by the substantial share dilution resulting from our October 2018 public offering. If we engage in a subsequent debt financing, we may be required to accept terms that restrict our ability to incur additional indebtedness, prohibit us from paying dividends, repurchasing our stock or making investments, and force us to maintain specified liquidity or other ratios, any of which could harm our business, operating results and financial condition. If we need additional capital and cannot raise it on acceptable terms, we may not be able to, among other things:

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Our failure to do any of these thingssuccessfully market our products could seriously harm our ability to execute our business strategy and may force us to curtail our research and development plans or existing operations.

We currently lack the funds to repay the convertible notes due in August 2018.

In March 2016, we entered into a 10% Senior Secured Convertible Note Purchase Agreement with the purchasers of the Notes. Accrued interest is payable semi-annually in cash or in kind through the issuance of identical new Notes, or with a combination of the two, at our option.  Through February 2017, we have made the interest payments in-kind through the issuance of additional notes totaling approximately $765,000.  The notes are secured by substantially all of our assets.  If we fail to pay the Notes, including accrued interest, in full when due, the holders of the Notes, acting through their agent, will be entitled to pursue all of their remedies as secured creditors, including taking possession of the collateral securing the Notes and effecting a private sale of some or all of our assets securing the Notes. After the holders of the Notes take such actions, we may not have enough assets to make payments owed to other creditors, to continue operating our business, or distribute any funds to stockholders.

Our success depends upon the networking and communications systems markets’ acceptance of our ICs.

The future prospects of our business depend onICs by equipment suppliers to the adoptioncloud networking, security and acceptance by our target markets, networking communications and data center equipment providers, of our Bandwidth Engine and LineSpeed ICs. In 2011, we began focusing our engineering, marketing and sales efforts on our IC products and de-emphasizing our technology licensing activities, which historically have been our primary revenue source.other systems markets. Our prospective customers may be unwilling to adopt and design-in our ICs due to the uncertainties and risks surrounding designing a new IC into their systems and relying on a supplier that has almost noa limited history of manufacturing such ICs. In addition,For example, our BandwidthAccelerator Engine IC products require our customers and their other IC suppliers to implement our new and proprietary GigaChip chip-to-chip communication protocol, GCI, which they may be unwilling to do. WeIn the past, we have determined and negotiated prices with a fewexperienced reluctance by potential customers forto adopt our ICs and have gained only limited experience with the cost of making and selling these products.GigaChip interface. Thus, currently, we do not know whether we will be able to profitably makegenerate adequate profit from making and sell theseselling our products. We are investing significant resources to develop our next generation IC products, but may not introduce these new products successfully or obtain significant revenue from them.

An important part of our strategy to gain market acceptance is to penetrate new markets by targeting market leaders to accept our IC solutions. This strategy is designed to encourage other participants in those markets to follow these leaders in adopting our solutions. If a high-profile industry participant adopts our ICs for one or more of its products but fails to achieve success with those products, or is unable to successfully implement our ICs, other industry participants’ perception of our solutions could be harmed. Any such event could reduce the amount of future sales of our IC products.

Our futureFuture revenue growth depends on our winning designs with ourexisting and new customers, retaining current customers, and having those customers designingdesign our solutions into their product offerings and successfully selling and marketing such products. If we do not continue to win designs in the short term, our product revenue in the following years will not grow.

We sell our ICs to original equipment manufacturer (OEM)OEM customers that include our ICs in their products. Our technology is generally incorporated into products at the design stage, which we refer to as a design win, and which we define as the point at which a customer has made a commitment to build a board against a fixed schematic for hisits system, and this board will utilize our ICs. As a result, our future revenue depends on our OEM customers designing our ICs into their products, and on those products being produced in volume and successfully commercialized. If we fail to retain our current customers or convince our current or prospective customers to include our ICs in their products and fail to achieve a consistent number of design wins, our results of operations and business will be harmed. In addition, if a current or prospective customer designs a competitor’s offering into its product, it becomes significantly more difficult for us to sell our IC solutions to that customer because changing suppliers involves significant cost, time, effort and risk for the OEM. Even if a customer designs one of our ICs into its product, we cannot be assured that the OEM’s product will be commercially

successful over time, or at all, or that we will receive or continue to receive any revenue from that customer. Furthermore, the customer product for which we obtain a design win may be canceled before the product enters production or before or after it is introduced into the market. Because of our extended sales cycle, our revenue in future years is highly dependent on design wins we are awarded today. Our lack of capital and uncertainty about our future technology roadmap also may limit our success in achieving additional design wins, as discussed under “Our auditor has expressed substantial doubt about our ability to continue as a going concern, and, absent additional financing, we may be unable to remain a going concern,” and “We may experience difficulties in transitioning to new wafer fabrication process technologies or in achieving higher levels of design integration, which may result in reduced manufacturing yields, delays in product deliveries and increased costs.”

The design win process is generally a lengthy, expensive and competitive process, with no guarantee of revenue, and, if we fail to generate sufficient revenue to offset our expenses, our business and operating results would suffer.

Achieving a design win is typically a lengthy, expensive and competitive process because our customers generally take a considerable amount of time to evaluate our ICs. In the markets we serve, the time from initial customer engagement to design win to production volume shipments can range from two to three years, though it may take longer for new customers or markets we intend to address. In order to win designs, we are required to both incur design and development costs and dedicate substantial engineering resources in pursuit of a single customer opportunity. Even though we incur these costs we may not prevail in the competitive selection process, and, even if we do achieve a design win, we may never generate sufficient, or any, revenue to offset our development expenditures. Our customers have the option to decide whether or not to put our solutions into production after initially designing our products in the specification. The customer can make changes to its product after a design win

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has been awarded to us, which can have the effect of canceling a previous design win. This occurred in 2018 when a large customer decided to phase out its use of our products. The delays inherent in our protracted sales cycle increase the risk that a customer will decide to cancel, curtail, reduce or delay its product plans, causing us to lose anticipated revenue. In addition, any change, delay or cancellation of a customer’s plans could harm our financial results, as we may have incurred significant expense while generating no revenue.

If our foundries do not achieve satisfactory yields or quality, our cost of goods soldnet revenue will increase, our operating margins will decline and our reputation and customer relationships could be harmed.

We depend not only on sufficient foundry manufacturing capacity and wafer prices, but also on good production yields (the number of good die per wafer) and timely wafer delivery to meet customer demand and maintain profit margins. The fabrication of our products is a complex and technically demanding process. Minor deviations in the manufacturing process can cause substantial decreases in yields and, in some cases, cause production to be suspended. Our foundry, Taiwan Semiconductor Manufacturing Company, (TSMC),or TSMC, from time to time, experiences manufacturing defects and reduced manufacturing yields. Changes in manufacturing processes or the inadvertent use of defective or contaminated materials by our foundries could result in lower than anticipated manufacturing yields, which would harm our revenue or increase our costs. For example, recently,in the past, our foundry produced ICs and met its process specification range but did not meet our customer’s specifications causing us to write off a portion of our production lot. Many of these problems are difficult to detect at an early stage of the manufacturing process and may be time consuming and expensive to correct. Poor yields from our foundry, or defects, integration issues or other performance problems in our ICs, could cause us significant customer relations and business reputation problems, harm our operating results and give rise to financial or other damages to our customers. Our customers might consequently seek damages from us for their losses. A product liability claim brought against us, even if unsuccessful, would likely be time consuming and costly to defend.

We may experience difficulties in transitioning to new wafer fabrication process technologies or in achieving higher levels of design integration, which may result in reduced manufacturing yields, delays in product deliveries and increased costs.

We aim to use the most advanced manufacturing process technology appropriate for our solutions that is available from TSMC. As a result, we periodically evaluate the benefits of migrating our solutions to other technologies in order to improve performance and reduce costs. These ongoing efforts require us from time to time to modify the manufacturing processes for our products and to redesign some products, which in turn may result in delays in product deliveries. We are dependent on TSMC to support the production of wafers for future versions of our ICs, as TSMC is our sole foundry. Such production may require changes to TSMC’s existing process technology. If TSMC elects to not alter their process technology to support future versions of our ICs, we would need to identify a new foundry.

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In addition, specifically with regard to our Bandwidth Engine products, our 1T-SRAM technology used in our Accelerator Engine products is not available at process nodes below 40 nanometers. To date, we have not developed any memory products below the 40 nanometer40-nanometer process node. To continue the product roadmap for our BandwidthAccelerator Engine and PSE products, we will need to identify a new foundry and/or no longer use our 1T-SRAM technology. We do not consider this to adversely affect our current product offerings, but we expect to face difficulties, delays and increased expense asif we transition our products to new processes and potentially to new foundries for future products. For example, we believe ourany next generation of products will need to be designed using a FinFETmore advanced process, which willwould require us to incur significantly high development costs for mask tooling and computer-aided design software. We currently lack the funds to pay for such development costs. Moreover, an inability to continue our product roadmap can adversely affect, and has in the past affected our efforts to win new customers, secure additional design wins and significantly grow our future revenues.

Because the manufacturing of integrated circuits is extremely complex, the process of qualifying a new foundry is a lengthy process and there can be no assurance that we will be able to find and qualify replacement suppliers without materially adversely affecting our business, financial condition, results of operations and prospects for future growth. We cannot assure you that we will be able to maintain our relationship with our foundriescurrent foundry or develop relationships with new foundries. If we or TSMC experience significant delays in transitioning to smaller geometries or fail to efficiently implement transitions, we could experience reduced manufacturing yields, delays in product deliveries and increased costs, any of which could harm our relationships with our customers and our operating results.

We may not achieve the anticipated benefits of becoming a fabless semiconductor company by developing and bringing to market the Bandwidth Engine and LineSpeedour IC product lines.products.

In 2010, we expanded our business model to become a fabless semiconductor company through the development of a product line of memory ICs called the Bandwidth Engine. In March 2013, we announced a product line of SerDes ICs called LineSpeed. Our goal is to increase our total available market by creating high-performance ICs for networking communications and data center systems using our proprietary technology and design expertise. ThisIn recent years, this development effort has required that we add headcount and design resources, such as expensive software tools, which has increased our losses from, and cash used in, operations. Due to our limited financial resources, we have been unable to sustain these development efforts and curtailed them in 2017. We may not be successful in our development efforts to bring our ICs to market successfully nor be successful in selling ICs due to various risks and uncertainties, including, but not limited to:

Our ICs have a lengthy sales cycle, which makes it difficult to predict success in this market and the timing of future revenue.

Our ICs have a lengthy sales cycle, ranging from six to 24 months from the date of our initial proposal to a prospective customer until the date on which the customer confirms that it has designed our product into its system. As lengthy, or anAn even lengthier period could ensue before we would know the volume of products that such customer will, or is likely to, order. A number of factors can contribute to the length of the sales cycle including technical evaluations of our products by the customers, the design process required to integrate our products into the customers’ products and the timing of the customers’ new product announcements. In anticipation of product orders, we may incur substantial costs before the sales cycle is complete and before we receive any customer payments. As a result, in the event that a sale is not completed or is cancelled or delayed, we may have incurred substantial expenses, making it more difficult for us to become profitable or otherwise negatively impacting our financial results. Furthermore, because of this lengthy sales cycle, the recording of revenues from our selling efforts may be substantially delayed, our ability to forecast our future revenue may be more limited and our revenue may fluctuate significantly from quarter to quarter. We cannot provide any assurances that our efforts to build a strong and profitable business based on the sale of ICs will succeed. If these efforts are not successful, in light of the substantial resources that we have invested, our future operating results and cash flows could be materially and adversely affected.

The semiconductor industry is cyclical in nature and subject to periodic downturns, which can negatively affect our revenue.

The semiconductor industry is cyclical and has experienced pronounced downturns for sustained periods of up to several years. To respond to any downturn, many semiconductor manufacturers and their customers will slow their research and development activities, cancel or delay new product developments, reduce their workforces and inventories and take a cautious approach to acquiring new equipment and technologies. As a result, our business has been in the past and could be adversely affected in the future by an industry downturn which could negatively impact our future revenue and profitability. Also, the cyclical nature of the semiconductor industry may cause our operating results to fluctuate significantly from year-to-year, which may tend to increase the volatility of the price of our common stock.year-to-year.

We expect our licensing and royalty revenues to decrease compared with our historical results, and there is no guarantee revenues from our IC products will replace these lost revenues in the near future.

In 2011, we began to place greater emphasis on our IC business and re-deploy engineering, marketing and sales resources from IP to IC activities. We are no longer actively pursuing new license arrangements for our 1T-SRAM technologies, and, as a result, our licenseroyalty and royaltyother revenues in 20162018 declined when compared with prior years. We do not expect to generate sufficient revenues from our IC business to allow us to achieve profitability in 2017. In addition, the production volumes of the current royalty-bearing products shipped by our licensees are expected to decrease; therefore we expect our royalty revenue to decrease in 20172020 and future periods. Historically, royalties have generated a 100% gross margin, and any decrease in royalties adversely affects our gross margin, operating results and cash flows.

Our revenue has been highly concentrated among a small number of licensees and customers, and our results of operations could be harmed if we lose a key revenue source and fail to replace it.

Our overall revenue has been highly concentrated, with a few customers accounting for a significant percentage of our total revenue.  For the year ended December 31, 2016,2019, our three largest customers represented 47%30%, 21%17% and 13%14% of total revenue, respectively. For the year ended December 31, 2015,2018, our three largest customers represented 34%32%, 31%18% and 12% of total revenue, respectively. For the year ended December 31, 2014, our three largest customers represented 34%, 31% and 11%18% of total revenue, respectively. We expect that a relatively small number of customers will continue to account for a substantial portion of our revenue for the foreseeable future.

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As a result of this revenue concentration, our results of operations could be adversely affected by the decision of a single key licensee or customer to cease using our technology or products or by a decline in the number of products that incorporate our technology that are sold by a single licensee or customer or by a small group of licensees or customers.

Our revenue concentration may also pose credit risks which could negatively affect our cash flow and financial condition.

We might also face credit risks associated with the concentration of our revenue among a small number of licensees and customers. As of December 31, 2016,2019, four customers represented 88%85% of total trade receivables. Our failure to collect receivables from any customer that represents a large percentage of receivables on a timely basis, or at all, could adversely affect our cash flow or results of operations and might cause our stock price to fall.operations.

Our products must meet exact specifications and defects and failures may occur, which may cause customers to return or stop buying our products.

Our customers generally establish demanding specifications for quality, performance and reliability that our products must meet. However, our products are highly complex and may contain defects and failures when they are first introduced or as new versions are released. If defects and failures occur in our products during the design phase or after, we could experience lost revenues, increased costs, including warranty and customer support expenses and penalties for non-performance stipulated in customer purchase agreements, delays in or cancellations or rescheduling of orders or shipments, product returns or discounts, diversion of management resources or damage to our reputation and brand equity, and in some cases consequential damages, any of which would harm our operating results. In addition, delays in our ability to fill product orders as a result of quality control issues may negatively impact our relationship with our customers. We cannot assure you that we will have sufficient resources to satisfy any asserted claims. Furthermore, any such defects, failures or delays may be particularly damaging to us as we attempt to establish our reputation as a reliable provider of IC products.

Because we sell our products on a purchase order basis and rely on estimated forecasts of our customers’ needs, inaccurate forecasts could adversely affect our business.

We expect to sell our IC products pursuant to individual purchase orders rather than long-term purchase commitments. Therefore, we will rely on estimated demand forecasts, based upon input from our customers, to determine how much product to manufacture. Because our sales will beare based primarily on purchase orders, our customers may cancel, delay or otherwise modify their purchase commitments with little or no notice to us. For these reasons, we will generally have limited visibility regarding our customers’ product needs. In addition, the product design cycle for networking OEMs is lengthy and it may be difficult for us to accurately anticipate when they will commence commercial shipments of products that include our ICs.

Furthermore, if we experience substantial warranty claims, our customers may cancel existing orders or cease to place future orders. Any cancellation, delay or other modification in our customers’ orders could significantly reduce our revenue, cause our operating results to fluctuate from period to period and make it more difficult for us to predict our revenue. In the event of a cancellation or reduction of an order, we may not have enough time to reduce operating expenses to mitigate the effect of the lost revenue on our business.

If we overestimate customer demand for our products, we may purchase products from our manufacturers that we cannot sell. Conversely, if we underestimate customer demand or if sufficient manufacturing and testing capacity wereare unavailable, we would forego revenue opportunities and could lose market share in the markets served by our products and could incur penalty payments under our customer purchase agreements. In addition, our inability to meet customer requirements for our products could lead to delays in product shipments, force customers to identify alternative sources and otherwise adversely affect our ongoing relationships with our customers.

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We depend on contract manufacturers for a significant portion of our revenue from the sale of our IC products.

Many of our current and prospective OEM customers use third party contract manufacturers to manufacture their systems and these contract manufacturers purchase our products directly from us on behalf of the OEMs. Although we expect to work with our OEM customers in the design and development phases of their systems, these OEMs often give contract manufacturers some authority in product purchasing decisions. If we cannot compete effectively for the business of these contract manufacturers, or if any of the contract manufacturers that work with our OEM customers experience financial or other difficulties in their businesses, our revenue and our business could be adversely affected. For example, if a contract manufacturer becomes subject to bankruptcy proceedings, we may not be able to obtain our products held by the contract manufacturer or recover payments owed to us by the contract manufacturer for products

already delivered to the contract manufacturer. If we are unable to persuade contract manufacturers to purchase our products, or if the contract manufacturers are unable to deliver systems with our products to OEMs on a timely basis, our business would be adversely affected.

We rely on independent foundries and contractors for the manufacture, assembly, testing and packaging of our integrated circuits, and the failure of any of these third parties to deliver products or otherwise perform as requested could damage our relationships with our customers and harm our sales and financial results.

As a fabless semiconductor company, we rely on third parties for substantially all of our manufacturing operations. We depend on these parties to supply us with material in a timely manner that meets our standards for yield, cost and quality. We do not have long-term supply contracts with any of our suppliers or manufacturing service providers, and therefore they are not obligated to manufacture products for us for any specific period, in any specific quantity or at any specified price except as may be provided in a particular purchase order. Any problems with our manufacturing supply chain could adversely impact our ability to ship our products to our customers on time and in the quantity required which in turn could damage our customer relationships and impede market acceptance of our IC solutions.

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Our third partythird-party wafer foundries and testing and assembly vendors and sales offices are located in regions at high risk for earthquakes and other natural disasters. Any disruption to the operations of these foundries vendors and officesvendors resulting from earthquakes or other natural disasters could cause significant delays in the development, production, shipment and sales of our IC products.

TSMC, which manufactures our products, is located in Asia, as are other foundries we may use in the future. EAG, which handlesOur vendors that provide substrates and wafer sorting and handle the testing of our products isare headquartered in either Asia or the San Francisco Bay Area of California. Our primary engineering design center ismanufacturing operations are located in Santa Clara, California, and we have sales offices in Japan and China.San Jose, California. The risk of an earthquake in the Pacific Rim region is significant due to the proximity of major earthquake fault lines. In September 1999, a major earthquake in Taiwan affected the facilities of several major foundries and other vendors. As a result of this earthquake, these vendors suffered power outages and disruptions that impaired their production capacity. In September 2003 and February 2016, additional disruptive earthquakes occurred in Taiwan. The occurrence of additional earthquakes or other natural disasters could result in the disruption of the wafer foundry or assembly and test capacity of the third parties that supply these services to us and may impede our research and development efforts as well as our ability to market and sell our products. We may not be able to obtain alternate capacity on favorable terms, if at all.

We face risks related to health epidemics which could adversely affect our business and results of operations.

Our business could be materially adversely affected by a widespread outbreak of contagious disease, including the recent outbreak of respiratory illness caused by a novel coronavirus first identified in China, known as COVID-19. We rely on TSMC and other suppliers, manufacturers and subcontractors located in nearby Taiwan for the manufacturing of our products. The effects of this outbreak could include disruptions or restrictions on our employees’ ability to travel in Asia and other affected regions, as well as temporary closures of the facilities of our suppliers, customers, or other vendors in our supply chain, which could impact our business, interactions and relationships with our customers, third-party suppliers and contractors, and results of operations. In addition, a significant outbreak of contagious diseases in the human population could result in a widespread health crisis that could adversely affect the economies and financial markets of many countries, resulting in an economic downturn that could reduce the demand for our products and likely impact our results of operations.

Any claim that our products or technology infringe third party intellectual property rights could increase our costs of operation and distract management and could result in expensive settlement costs or the discontinuance of our technology licensing or product offerings. In addition, we may incur substantial litigation expense which would adversely affect our profitability.

The semiconductor industry is characterized by vigorous protection and pursuit of intellectual property rights or positions which has resulted in often protracted and expensive litigation. We are not aware of any third party intellectual property that our products or technology would infringe. However, like many companies of our size with limited resources, we have not searched for all potentially applicable intellectual property in the public databases. It is possible that a third party now has, or may in the future obtain, patents or other intellectual property rights that our products or technology may now, or in the future, infringe. Our licensees and IC customers, or we, might, from time to time, receive notice of claims that we have infringed patents or other intellectual property rights of others. Litigation against us can result in significant expense and divert the efforts of our technical and management personnel whether or not the litigation has merit or results in a determination adverse to us.

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The discovery of defects in our technology and products could expose us to liability for damages.

The discovery of a defect in our technologies and products could lead our customers to seek damages from us. Many of our agreements with customers include provisions waiving implied warranties regarding our technology and products and limiting our liability to our customers. We cannot be certain, however, that the waivers or limitations of liability contained in our agreements with customers will be enforceable.

Royalty amounts owed to us might be difficult to verify, and we might find it difficult, expensive and time-consuming to enforce our license agreements.

The standard terms of our 1T-SRAM license agreements require our licensees to document the manufacture and sale of products that incorporate our technology and generally report this data to us after the end of each quarter. We have the right to audit these royalty reports periodically, although we have not conducted any such audits since 2010.recently. These audits can be expensive, time-consuming and potentially detrimental to our business relationships. A failure to fully enforce the royalty provisions of our license agreements could cause our revenue to decrease and impede our ability to achieve and maintain profitability.

We might not be able to protect and enforce our intellectual property rights which could impair our ability to compete and reduce the value of our technology.

Our technology is complex and is intended for use in complex SoCsICs and networking systems. Our licensees’ products utilize our embedded memory and/or I/Ointerface technology and a large number of companies manufacture and market these products. Because of these factors, policing the unauthorized use of our intellectual property is difficult and expensive. We cannot be certain that we will be able to detect unauthorized use of our technology or prevent other parties from designing and marketing unauthorized products based on our technology. In the event we identify any past or present infringement of our patents, copyrights or trademarks, or any violation of our trade secrets, confidentiality procedures or licensing agreements, we cannot assure you that the steps taken by us to protect our proprietary information will be adequate to prevent misappropriation of our technology. Our inability to adequately protect our intellectual property would reduce significantly the barriers of entry for directly competing technologies and could reduce the value of our technology. Furthermore, we might initiate claims or litigation against third parties for infringement of our proprietary rights or to establish the validity of our proprietary rights. Litigation by us could result in significant expense and divert the efforts of our technical and management personnel whether or not such litigation results in a determination favorable to us.

Our existing patents might not provide us with sufficient protection of our intellectual property, and our patent applications might not result in the issuance of patents, either of which could reduce the value of our core technology and harm our business.

We rely on a combination of patents, trademarks, copyrights, trade secret laws and confidentiality procedures to protect our intellectual property rights. As of December 31, 2016, we held 67 patents in the United States, and approximately 36 foreign patents, which expire at various times from 2018 to 2035. In addition, as of December 31, 2016, we also held 18 pending patent applications worldwide. We cannot be sure that any patents will be issued from any of our pending applications or that any claims allowed from pending applications will be of sufficient scope or strength, or issued in all countries where our products can be sold, to provide meaningful protection or any commercial advantage to us. In December 2011, we sold 43 United States and 30 related foreign patents, which reduced the size of our patent portfolio and diminishes our ability to assert counterclaims in the defense of actions against us that may arise. Also, competitors might be able to design around our patents. Failure of our patents or patent applications to provide meaningful protection might allow others to utilize our technology without any compensation to us.

The discovery of defects in our technology and products could expose us to liability for damages.

The discovery of a defect in our technologies and products could lead our customers to seek damages from us. Many of our agreements with customers include provisions waiving implied warranties regarding our technology and products and limiting our liability to our customers. We cannot be certain, however, that the waivers or limitations of liability contained in our agreements with customers will be enforceable.

If we fail to retain key personnel, our business and growth could be negatively affected.

Our business has been dependent to a significant degree upon the services of a small number of executive officers and technical employees. The loss of key personnel could negatively impact our technology development efforts, our ability to deliver products under our existing agreements, maintain strategic relationships with our partners and obtain new customers. We generally have not entered into employment or non-competition agreements with any of our employees and do not maintain key-man life insurance on the lives of any of our key personnel.

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We may incur additional debt in the future, subject to certain limitations contained in our senior secured convertible notes.Senior Secured Convertible Notes.

The degree to which we are leveraged and the restrictions governing our indebtedness could have important consequences including, but not limited to:

Our stockholder rights plan could prevent stockholders from receiving a premium over the market price for their shares from a potential acquirer.

We adopted a stockholder rights plan that generally entitles our stockholders to rights to acquire additional shares of our common stock when a third party acquires 15% of our common stock or commences or announces its intent to commence a tender offer for at least 15% of our common stock, other than for one group of related stockholders, as to whom this threshold is 20%.stock. The plan also includes an exception to permit the acquisition of shares representing more than 15% of our common stock by a brokerage firm that manages independent customer accounts and generally does not have any discretionary voting power with respect to such shares. This plan could delay, deter or prevent an investor from acquiring us in a transaction that could otherwise result in stockholders receiving a premium over the market price for their shares of common stock. Our intention is to maintain and enforce the terms of this plan, which could delay, deter or prevent an investor from acquiring us in a transaction that could otherwise result in stockholders receiving a premium over the market price for their shares of common stock.

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Potential volatility of the price of our common stock could negatively affect your investment.

We cannot assure you that there will continue to be an active trading market for our common stock. Historically, the stock market, as well as our common stock, has experienced significant price and volume fluctuations. Market prices of securities of technology companies have been highly volatile and frequently reach levels that bear no relationship to the operating performance of such companies. These market prices generally are not sustainable and are subject to wide variations. If our common stock trades to unsustainably high levels, it is likely that the market price of our common stock will thereafter experience a material decline. In the past, our board of directors approved stock repurchase programs, and any future program could impact the price of our common stock and increase volatility.

In the past, securities class action litigation has often been brought against a company following periods of volatility in the market price of its securities. We could be the target of similar litigation in the future. Securities litigation could cause us to incur substantial costs, divert management’s attention and resources, harm our reputation in the industry and the securities markets and negatively impact our operating results.

Our stock price could drop, and there could be significantly less trading activity in our stock, if securities or industry analysts downgrade our stock or do not publish research or reports about our business.

Our stock price and the trading market for our stock are likely to be affected significantly by the research and reports concerning our company and our business which are published by industry and securities analysts. We do not have any influence or control over these analysts, their reports or their recommendations. Our stock price and the trading market for our stock could be negatively affected if any analyst downgrades our stock, publishes a report which is critical of our business, or discontinues coverage of us.

We are a “smaller reporting company” and, as a result of the reduced disclosure and governance requirements applicable to smaller reporting companies, our common stock may be less attractive to investors.

We are a “smaller reporting company,” meaning that we are not an investment company, an asset-backed issuer, or a majority-owned subsidiary of a parent company that is not a “smaller reporting company,” have a public float of less than $75 million and have annual revenues of less than $50 million during the most recently completed fiscal year.  As a “smaller reporting company,” we are subject to lesser disclosure obligations in our SEC filings compared to other issuers. Specifically, “smaller reporting companies” are able to provide simplified executive compensation disclosures in their filings, are exempt from the provisions of Section 404(b) of the Sarbanes-Oxley Act requiring that independent registered public accounting firms provide an attestation report on the effectiveness of internal control over financial reporting and have certain other decreased disclosure obligations in their SEC filings, including, among other things, only being required to provide two years of audited financial statements in annual reports. Decreased disclosures in our SEC filings due to our status as a “smaller reporting company” may make it harder for investors to analyze our operating results and financial prospects.

If we fail to maintain compliance with the continued listing requirements of the Nasdaq CapitalStock Market, our common stock may be delisted and the price of our common stock and our ability to access the capital markets could be negatively impacted.

Our common stock currently trades on The NASDAQthe Nasdaq Stock Market (Nasdaq) under the symbol “MOSY.” This market has continued listing standards that we must comply with in order to maintain the listing of our common stock. The continued listing standards include, among others, a minimum bid price requirement of $1.00 per share and any of: (i) a minimum stockholders’ equity of $2.5 million; (ii) a market value of listed securities of at least $35.0 million; or (iii) net income from continuing operations of $500,000 in the most recently completed fiscal year or in the two of the last three fiscal years. Our results of operations and fluctuating stock price directly impact our ability to satisfy these continued listing standards. In the event we are unable to maintain these continued listing standards, our common stock may be subject to delisting from the Nasdaq CapitalStock Market.

On July 14, 2016, we received a deficiency letter from the Listing Qualifications Department (the Staff) of Nasdaq providing notification that the Company was not in compliance with Nasdaq’s audit committee composition requirements pursuant to Nasdaq Listing Rule 5605(c)(2).  Nasdaq Listing Rule 5605 requires a listed company to have an audit committee comprised of at least three independent members and, during 2016, the number of independent directors on our Audit Committee was reduced from three to two.

The letter also states that we will be provided: (i) until the earlier of our next annual shareholders’ meeting or June 24, 2017. If we do not regain compliance during this period, then the Staff will provide notice that our securities will be subject to delisting. At such time, we may appeal the delisting determination to a Nasdaq Listing Qualifications Panel (Panel). We would remain listed pending the Panel’s decision. There can be no assurance that, if we do appeal a subsequent delisting determination by the Staff to the Panel, that such appeal would be successful.

In addition, due to the recent resignation of a director, we no longer have at least two independent members serving on the compensation committee of the board of directors. We intend to fill the vacant board of directors and committee seats prior to our next annual meeting of shareholders.

If we arewere to be delisted, we would expect our common stock to be traded in the over-the-counter market which could adversely affect the liquidity of our common stock. Additionally, we could face significant material adverse consequences, including:

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PartPart II

Item 5.  Market for Registrant’s Common Equity, Related Stockholder Matters and Issuer Purchases of Equity Securities

Our common stock is currently listed on the Capital Market of the NASDAQ Stock Market under the symbol MOSY. The following table sets forth the range

Holders of high and low sales pricesRecord

As of our common stock for each period indicated. The table has been modified to reflect the impact of a 1-for-10 reverse stock split effected February 16, 2017.  See Note 1 of the consolidated financial statements in Item 15 for further discussion of the reverse stock split.

We had 15 stockholders of record as of March 1, 2017.

Dividend Policy

We have not declared or paid any cash dividends on our common stock and presently intend to retain future earnings, if any, to fund the development and growth of our business and, therefore, do not anticipate paying any cash dividends in the foreseeable future.

Stock Performance Graph

The following graph compares cumulative total stockholder return on our common stock with that of the S&P 500 Index and the S&P Technology Sector Index from 2011 through 2016. The comparison assumes that $100 was invested on December 31, 2011 in our common stock, the stocks included in the S&P 500 Index and the stocks included in the S&P Technology Sector Index. We have never paid any cash dividends to2019, there were three holders of our common stock.

The comparisons shown in the graph below are based upon historical data, and we caution that the stock price performance shown in the graph below is not indicative of, nor intended to forecast, the potential future performancerecord of our common stock. Information usedThe actual number of stockholders is significantly greater than this number of record stockholders and includes stockholders who are beneficial owners but whose shares are held in the graph was obtained from Standardstreet name by brokers and Poor’s website, a source believed toother nominees. This number of stockholders of record also does not include stockholders whose shares may be reliable, but we are not responsible for any errors or omissionsheld in such information.

Comparison of Five-Year Cumulative Return

trust by other entities.

Securities Authorized for Issuance under Equity Compensation Plan

For information regarding securities authorized for issuance under equity compensation plans, please refer to Item 12.—12—Security Ownership of Certain Beneficial Owners and Management and Related Stockholder Matters.

Item 6.  Selected Financial Data

The selected financial data presented below is derived from our consolidated financial statements that are included under Item 15. The selected financial data should be read in conjunction with our consolidated financial statements and notes related to those statements and with “Management’s Discussion and Analysis of Financial Condition and Results of Operations” included herein. The table has been modified to reflect the impact of a 1-for-10 reverse stock split effected February 16, 2017.  See Note 1 of the consolidated financial statements for further discussion of the reverse stock split.Not applicable.

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Item 7.  Management’s Discussion and Analysis ofof Financial Condition and Results of Operations

This Management’s Discussion and Analysis of Financial Condition and Results of Operations should be read in conjunction with the accompanying consolidated financial statements and notes included in this report.

Overview

Our strategy and primary business objective is to becomebe a profitable IP-rich fabless semiconductor company focused on the developmentoffering ICs and sale of integrated circuits, or ICs,related software and IP that deliver unparalleled memory bandwidth and access rate performance for the high-speedhigh-performance data processing in cloud networking, communications, storagesecurity appliances, video, test and monitoring, and data center markets.systems. Our solutions deliver time-to-market, performance, power, area and economic benefits for system original equipment manufacturers, or OEMs. We have developed two families of ICsOur primary product line is marketed under the BandwidthAccelerator Engine® name and LineSpeed™ product names.comprises our Bandwidth Engine ICs combineand Programmable HyperSpeed Engine IC products, which integrate our proprietary, 1T-SRAM® high-density embedded memory integrated macroand a highly-efficient serial interface protocol resulting in a monolithic memory IC solution optimized for memory bandwidth and transaction access performance.  Our second-generation Bandwidth Engine, or Bandwidth Engine 2, products are expected to be our primary revenue source through at least 2021, and we expect these products to continue to generate significant revenue thereafter.  As we are not developing new IC products, from a product development perspective, we continue to leverage our current technologies and core competencies to expand our product offerings without incurring significant additional R&D expenses. Recently, we announced our new Software Accelerator product line consisting of software and IP available for license. This new product line will include multiple function accelerator platform products, which target specific application functions and high-speed serialwill use a common software interface to allow performance scalability over multiple hardware environments. These function accelerator platform products are hardware agnostic and operate with or SerDes, I/O, withwithout one of our intelligent accessAccelerator Engine ICs. This software-defined, hardware-accelerated platform architecture utilizes an internally developed graphical memory engine architecture to provide flexible data classification and analysis capability. We believe the technology will generate new opportunities that require less up-front architectural changes by system designers and provide a highly efficient interface protocol. The LineSpeedscalable performance roadmap of options using our Accelerator Engine ICs. We expect our initial software accelerator products to be available for license in the first half of 2020. Despite our limited new IC product line, which was announced in March 2013, is comprised of non-memory, high-speed SerDes I/O devices with clock data recovery, gearboxdevelopment efforts, we believe our current hardware and retimer functionality, which convert lanes of data received on line cards or by optical modules into different configurations and/or ensure signal integrity. Historically, our primary business was the design,software/firmware product portfolio positions us for future growth and profitability.  We will continue to seek third-party funding for new product development marketing, sale and support of differentiated intellectual property, or IP, including embedded memory and high-speed parallel and SerDes I/O used in advanced systems-on-chips, or SoCs. Currently, we are focused on developing differentiated IP-rich IC products and are dedicating all our research and development, marketing and sales budget to these IC products.efforts.

Our future success and ability to achieve and maintain profitability are dependent on the marketing and sales of our IC products into networking, communications and other markets requiring high-bandwidth memory access.

We incurred net losses of approximately $32$2.6 million and $31$11.4 million for the years ended December 31, 20162019 and 2015,2018, respectively, and had an accumulated deficit of approximately $214$238 million as of December 31, 2016.  2019.  These and prior year losses have resulted in significant negative cash flows for almost a decade and have necessitated that we raise substantial amounts of additional capital during this period. To date, we have primarily financed our operations through multiple offerings of common stock to investors and affiliates, as well as asset sale transactions. In March 2016, we entered into a 10% Senior Secured Convertible Note Purchase Agreement with the purchaserstransactions and one offering of $8 million principal amount of 10% Senior Secured Convertible Notes due August 15, 2018 (the Notes), at par, in a private placement transaction. The Notes bear interest at the annual rate of 10%. Accrued interest is payable semi-annually in cash or in kind through the issuance of identical new Notes, or with a combination of the two, at our option. Through February 2017, we have made the interest payments in-kind through the issuance of additional notes totaling approximately $0.8 million.  Further, the Notes restrict our ability to incur any indebtedness for borrowed money, unless such indebtedness by its terms is expressly subordinated to the Notes in right of payment and to the security interest of the Note holder(s) in respect to the priority and enforcement of any security interest in property of the Company securing such new debt; provided that the Note holder(s) security interest and cash payment rights under the Notes shall be subordinate to a maximum of $5 million of indebtedness for a secured accounts receivable line of credit facility under certain conditions. (See Note No. 11, Convertible Notes)convertible notes.

We expect tomay continue to incur operating losses for the foreseeable future as we secure customers for and continues to invest in the commercialization of our IC products. Due to the strong commitment of our resources to research and development and expansion of its product offerings to customers, we will need to increase revenues substantially beyond levels that we have attained in the past in order to generate sustainable operating profit and sufficient cash flows to continue doing business without raising additional capital from time to time. As a result of our expected operating losses and cash burn for the foreseeable future, recurring losses from operations, and the need to repay the Notes and accrued interest in 2018, if we are unable to raise sufficient capital through additional debt or equity arrangements, there will be uncertainty regarding our ability to maintain liquidity sufficient to operate our business effectively, which raises substantial doubt as to our ability to continue as a going concern within one year from the date of issuance of these financial statements. These financial statements do not include any adjustments that might result from this uncertainty. There can be no assurance that such additional capital, whether in the form of debt or equity financing, will be sufficient or available and, if available, that such capital will be offered on terms and conditions acceptable to us. We are exploring various alternatives, and expect to implement cost reductions to successfully sustain

the business.  If we are unsuccessful in these efforts, we will need to implement significant cost reduction strategies that could affect our near- and long-term business plan. These efforts may include, but are not limited to: reducing headcount and curtailing business activities, especially around new product development.

Critical Accounting Policies and Use of Estimates

Our consolidated financial statements are prepared in conformity with accounting principles generally accepted in the United States of America. Note 1 to the consolidated financial statements in Item 15 of this report describes the significant accounting policies and methods used in the preparation of our consolidated financial statements.

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We have identified the accounting policies below as some of the more critical to our business and the understanding of our results of operations. These policies may involve estimates and judgments that affect the reported amounts of assets, liabilities, revenues and expenses. Although we believe our judgments and estimates are appropriate, actual future results may differ from our estimates, and if different assumptions or conditions were to prevail, the results could be materially different from our reported results.

Revenue Recognition

GeneralWe adopted Financial Accounting Standards Board (“FASB”) Accounting Standards Codification Topic 606, Revenue from Contracts with Customers and all its related amendments (“ASC 606”), on January 1, 2018 using the modified retrospective method. We recognized the cumulative effect of initially applying the new revenue standard as an adjustment to the opening balance of accumulated deficit as of January 1, 2018. The comparative information for 2017 has not been recast and continues to be reported under the accounting standards in effect for that period. See Note 1 to the consolidated financial statements in Item 15 of this report for an additional description of our recognition of the cumulative effect upon the adoption of ASC 606.

We generate revenue primarily from the sales of IC products and licensing of our IP. Weintellectual property. Revenues are recognized when control is transferred to customers in amounts that reflect the consideration we expect to be entitled to receive in exchange for those goods. Revenue recognition is evaluated through the following five steps: (i) identification of the contract, or contracts, with a customer; (ii) identification of the performance obligations in the contract; (iii) determination of the transaction price; (iv) allocation of the transaction price to the performance obligations in the contract; and (v) recognition of revenue when or as a performance obligation is satisfied.      

IC products

Revenue is recognized when performance obligations under the terms of a contract with a customer are satisfied.

The majority of our contracts have a single performance obligation to transfer products. Accordingly, we recognize revenue when persuasive evidencetitle and risk of an arrangement exists, deliveryloss have been transferred to the customer, generally at the time of shipment of products. Revenue is measured as the amount of consideration we expect to receive in exchange for transferring products and is generally based upon a negotiated, formula, list or performance has occurred, the sales price is fixed or determinable, and collectibility is reasonably assured. Evidence of an arrangement generally consists of signed agreements or customer purchase orders.

IC Products

Products are soldprice. We sell our products both directly to customers as well asand through distributors. Revenue from sales directly to customers isdistributors generally recognized at the time of shipment. under agreements with payment terms typically 60 days or less.  

We may record an estimated allowance, at the time of shipment, for future returns and other charges against revenue consistent with the terms of sale.  IC product

Royalty and other

Our licensing contracts typically provide for royalties based on the licensee’s use of our memory technology in its currently shipping commercial products. With the adoption of ASC 606 in January 2018, we estimate our royalty revenue and costs relating to sales made through distributors with rights of return or stock rotation are generally deferred until the distributors sell the product to end customers due to our inability to estimate future returns and credits to be issued. Distributors are generally able to return up to 10% of their purchases of slow, non-moving or obsolete inventory for credit every six months. At the time of shipment to distributors, an accounts receivable for the selling price is recorded, as there is a legally enforceable right to receive payment, and inventory is relieved, as legal title to the inventory is transferred upon shipment. Revenues are recognized upon receiving notification from the distributors that products have been sold to end customers. Distributors provide information regarding products and quantity, end customer shipments and remaining inventory on hand. The associated deferred margin is included in the accrued expenses and other line item in the consolidated balance sheets.

Royalty

Royalty revenue represents amounts earned under provisions in our memory licensing agreements that require our licensees to report royalties and make payments at a stated rate based on actual units manufactured or sold by licensees for products that include our memory IP. Our license agreements require the licensee to report the manufacture or sale of products that include our technology after the end of thecalendar quarter in which the sale or manufacture occurs. We recognize royaltieslicensee uses the licensed technology.  Payments are received in the subsequent quarter in which we receive the licensee’s report. The timing and level of royalties are difficult to predict, and depend on the licensee’s ability to market, produce and sell products incorporating our technology.

Licensing

Licensing revenue consists of fees earned from license agreements, development services and support and maintenance. For stand-alone license agreements or license deliverables in multi-deliverable arrangements that do not require significant development, modification or customization, revenue is recognized when all revenue recognition criteria have been met. Delivery of the licensed technology is typically the final revenue recognition criterion met, at which time revenue is recognized. If any of the criteria are not met, revenue recognition is deferred until such time as all

criteria have been met. Support and maintenance revenue is recognized ratably over the period during which the obligation exists, typically 12 months.

Fair Value Measurements of Financial Instruments

We measure the fair value of financial instruments using a fair value hierarchy that prioritizes the inputs to valuation techniques used to measure fair value into three broad levels, as follows:

Level 1—Inputs used to measure fair value are unadjusted quoted prices that are available in active markets for the identical assets or liabilities as of the reporting date.

Level 2—Pricing is provided by third party sources of market information obtained from investment advisors rather than models. We do not adjust for or apply any additional assumptions or estimates to the pricing information we receive from advisors. Our Level 2 securities include cash equivalents and available-for-sale securities, which consisted primarily of corporate debt, and government agency and municipal debt securities from issuers with high quality credit ratings. Our investment advisors obtain pricing data from independent sources, such as Standard & Poor’s, Bloomberg and Interactive Data Corporation, and rely on comparable pricing of other securities because the Level 2 securities we hold are not actively traded and have fewer

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observable transactions. We consider this the most reliable information available for the valuation of the securities.

Level 3—Unobservable inputs that are supported by little or no market activity and reflect the use of significant management judgment are used to measure fair value. These values are generally determined using pricing models for which the assumptions utilize management’s estimates of market participant assumptions. The determination of fair value for Level 3 investments and other financial instruments involves the most management judgment and subjectivity.

Valuation of long-lived Assets

We evaluate our long-lived assets for impairment at least annually, or more frequently when a triggering event is deemed to have occurred. This assessment is subjective in nature and requires significant management judgment to forecast future operating results, projected cash flows and current period market capitalization levels. If our estimates and assumptions change in the future, it could result in a material write-down of long-lived assets. We amortize our finite-lived intangible assets, such as developed technology and patent license, on a straight-line basis over their estimated useful lives of three to seven years. We recognize an impairment charge as the difference between the net book value of such assets and the fair value of the assets on the measurement date.

Goodwill

We determine the amount of potential goodwill impairment by comparing the fair value of the reporting unit with its carrying amount. To the extent the carrying value of a reporting unit exceeds its fair value, a goodwill impairment charge is recognized. We have determined that we have a single reporting unit for purposes of performing our goodwill impairment test. As we use the market approach to determine the step one fair value, the price of our common stock is an important component of the fair value calculation. We review goodwill for impairment on an annual basis or whenever events or changes in circumstances indicate the carrying value of an asset may not be recoverable. We first assess qualitative factors to determine whether it is more-likely-than-not that the fair value of the reporting unit is less than the carrying amount as a basis for determining whether it is necessary to perform the two-stepan impairment test. If the qualitative assessment warrants further analysis, we compare the fair value of the reporting unit to its carrying value. The fair value of the reporting unit is determined using the market approach. If the fair value of the reporting unit exceeds the carrying value of net assets of the reporting unit, goodwill is not impaired, and no further testing is performed. If the carrying value of the reporting unit’s goodwill exceeds its implied fair value, then we must record an impairment charge equal to the difference.

We have determined that we have a single reporting unitperformed our annual test for purposes of performing the goodwill impairment test. We use the market approach to assess impairment in the second stepas of the analysis. We performed the annual impairment test in September 2016,1, 2019, and, the test did not indicate impairment of goodwill.

During the fourth quarter of 2016, we concluded a triggering event had occurred due to a sustained decrease in the price per share of our common stock, and related reduced market capitalization. We performed the first step of the impairment test to identify potential goodwill impairment, and the test results indicated the goodwill carrying value was greater than its implied fair value. We then performedFurther, the Company concluded a step-two analysis to compare the carrying amount of goodwilltriggering event had occurred due to the sustained decrease in the price per share of its common stock and related reduced market capitalization as of September 30, 2019 and performed an additional test for impairment of its goodwill asset resulting in further indication that the goodwill carrying value was still greater than its implied fair value of the goodwill, and we determined the estimated fair values of the assets and liabilities of its single reporting unit. The fair values of the assets and liabilities identified in the impairment test were determined using the

combination of the income approach and the market approach. The implied fair value of goodwill was measured as the excess of the fair value of our single reporting unit over the fair value of its assets and liabilities.value. As a result of both of these tests, the step-two test, weCompany recorded a non-cash impairment chargecharges of $9,858,000$0.4 million during the fourththird quarter of 2016.2019.  As a result of these charges, the Company’s goodwill balance was reduced to zero as of September 30, 2019.

Deferred tax valuation allowance

When we prepare our consolidated financial statements, we estimate our income tax liability for each of the various jurisdictions where we conduct business. This requires us to estimate our actual current tax exposure and to assess temporary differences that result from differing treatment of certain items for tax and accounting purposes. These differences result in deferred tax assets, which we show on our consolidated balance sheet under the category of other current assets. The net deferred tax assets are reduced by a valuation allowance if, based upon weighted available evidence, it is more likely than not that some or all of the deferred tax assets will not be realized. We must make significant judgments to determine our provision for income taxes, our deferred tax assets and liabilities and any valuation allowance to be recorded against our net deferred tax asset. We believe that utilization of our net operating loss and tax credit carryforwards, which comprise the majority of our deferred tax assets, may be subject to a substantial annual limitation due to the ownership change limitations provided by the Internal Revenue Code and similar state provisions. See Note 4 to the consolidated financial statements in Item 15 of this report for an additional description of these limitations.

Stock-based compensation

We recognize stock-based compensation for equity awards on a straight-line basis over the requisite service period, usually the vesting period, based on the grant-date fair value. We estimate the value of employee stock

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options on the date of grant using the Black-Scholes model. The determination of fair value of share-based payment awards on the date of grant using an option-pricing model is affected by our stock price, as well as assumptions regarding a number of highly complex and subjective variables. These variables include, but are not limited to, the expected stock price volatility over the term of the awards, and actual and projected employee stock option exercise behaviors. The expected term of options granted is derived from historical data on employee exercises and post-vesting employment termination behavior. The expected volatility is based on the historical volatility of our stock price.

Results of Operations

Net Revenue

royalty revenue.

Cost of Net Revenue and Gross Profit

2020.

Selling, General and Administrative (SG&A)