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United Micro Electronics (UMC)

Utility
Method of Fabricating a Flash Memory
25 Nov 20
A method of fabricating a semiconductor device includes forming a memory gate and a hard mask layer on the memory gate, forming a select gate on a sidewall of the memory gate and the hard mask layer, performing a selective oxidation process to form an oxide layer on the hard mask layer and the select gate, wherein a portion of the oxide layer on the select gate is thicker than a portion of the oxide layer on the hard mask layer, and removing the oxide layer on the hard mask layer and the hard mask layer to expose a top surface of the memory gate.
WEI XU, WENBO DING, Yu-Yang Chen, Wang Xiang
Filed: 19 May 19
Utility
Manufacturing Method of Semiconductor Structure
25 Nov 20
A manufacturing method of the semiconductor structure including the following is provided.
Zhenhai Zhang
Filed: 9 Aug 20
Utility
Metal Interconnect Structure and Method for Fabricating the Same
25 Nov 20
A method for fabricating metal interconnect structure includes the steps of: forming a first metal interconnection in a first inter-metal dielectric (IMD) layer on a substrate; forming a cap layer on the first metal interconnection; forming a second IMD layer on the cap layer; performing a first etching process to remove part of the second IMD layer for forming an opening; performing a plasma treatment process; and performing a second etching process to remove polymers from bottom of the opening.
Yi-How Chou, Tzu-Hao Fu, Tsung-Yin Hsieh, Chih-Sheng Chang, Shih-Chun Tsai, Kun-Chen Ho, Yang-Chou Lin
Filed: 11 Aug 20
Utility
Structure of Memory Device and Fabrication Method Thereof
25 Nov 20
A structure of a memory device and a fabrication method thereof are provided.
Liang Yi, Zhiguo Li, Chi Ren
Filed: 24 Jun 19
Utility
Semiconductor Device and Method for Fabricating the Same
25 Nov 20
A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first liner on the MTJ; forming a second liner on the first liner; forming an inter-metal dielectric (IMD) layer on the MTJ, and forming a metal interconnection in the IMD layer, the second liner, and the first liner to electrically connect the MTJ.
Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
Filed: 11 Jun 19
Utility
Semiconductor Device and Method for Fabricating the Same
25 Nov 20
A semiconductor device includes: a magnetic tunneling junction (MTJ) on a substrate; a first inter-metal dielectric (IMD) layer around the MTJ; a metal interconnection on and directly contacting the MTJ; a second IMD layer on the first IMD layer and around the metal interconnection; and a metal oxide layer on the second IMD layer and around the metal interconnection.
Chih-Wei Kuo, Meng-Jun Wang, Yi-Wei Tseng, Yu-Tsung Lai, Jiunn-Hsiung Liao
Filed: 12 Jun 19
Utility
Semiconductor device and method for planarizing the same
23 Nov 20
A semiconductor device includes a substrate, having a cell region and a core region.
Chia-Hung Chen, Yu-Huang Yeh, Chuan-Fu Wang, Chin-Chin Tsai
Filed: 31 Oct 18
Utility
Interconnect structure, interconnect layout structure, and manufacturing method thereof
23 Nov 20
A method for manufacturing an interconnect structure with air gaps includes the following steps.
Tong-Yu Chen, Chia-Fang Lin
Filed: 13 Mar 19
Utility
Semiconductor device and method to fabricate the semiconductor device
23 Nov 20
A structure of semiconductor device includes a substrate, having a dielectric layer on top.
Da-Jun Lin, Bin-Siang Tsai, San-Fu Lin
Filed: 29 Mar 20
Utility
Method for forming semiconductor device having a multi-thickness gate trench dielectric layer
23 Nov 20
A semiconductor device includes a semiconductor substrate having a gate trench including of an upper trench and a lower trench.
Tsuo-Wen Lu, Ger-Pin Lin, Tien-Chen Chan, Shu-Yen Chan
Filed: 17 Jun 19
Utility
Layout pattern of a static random access memory
23 Nov 20
A layout pattern of a static random access memory (SRAM) preferably includes a first inverter and a second inverter.
Chun-Hsien Huang, Ching-Cheng Lung, Yu-Tse Kuo, Shu-Ru Wang, Chun-Yen Tseng
Filed: 4 Oct 18
Utility
Semiconductor memory device and fabrication method thereof
23 Nov 20
The disclosure provides a semiconductor memory device including a substrate having a memory cell region and an alignment mark region; a dielectric layer covering the memory cell region and the alignment mark region; conductive vias in the dielectric layer within the memory cell region; an alignment mark trench in the dielectric layer within the alignment mark region; and storage structures disposed on the conductive vias, respectively.
Hui-Lin Wang, Chia-Chang Hsu, Chen-Yi Weng, Hung-Chan Lin, Jing-Yin Jhang, Yu-Ping Wang
Filed: 8 Dec 18
Utility
Semiconductor device and method for fabricating the same
23 Nov 20
A semiconductor device includes: a magnetic tunneling junction (MTJ) on a substrate; a first inter-metal dielectric (IMD) layer around the MTJ; a metal interconnection on and directly contacting the MTJ; a second IMD layer on the first IMD layer and around the metal interconnection; and a metal oxide layer on the second IMD layer and around the metal interconnection.
Chih-Wei Kuo, Meng-Jun Wang, Yi-Wei Tseng, Yu-Tsung Lai, Jiunn-Hsiung Liao
Filed: 12 Jun 19
Utility
Two-port Ternary Content Addressable Memory and Layout Pattern Thereof, and Associated Memory Device
18 Nov 20
A two-port ternary content addressable memory (TCAM) and layout pattern thereof, and associated memory device are provided.
Chun-Hsien Huang, Ching-Cheng Lung, Yu-Tse Kuo, Shu-Ru Wang, Chun-Yen Tseng
Filed: 11 Jun 19
Utility
Mark Pattern In Semiconductor Device
18 Nov 20
A mark pattern includes unit cells immediately adjacent to each other and arranged in a form of dot matrix to form a register mark or an identification code, wherein each unit cell has configuration identical to functional devices of pMOS and nMOS, and each unit cell includes a first active region, a second active region isolated from the first active region, and first gate structures extending along a first direction and are arranged along a second direction perpendicular to the first direction, and the first gate structures straddling the first active region and the second active region, contact structures disposed between the first gate structures on the first active region and the second active region, and via structures disposed on the contact structures and two opposite ends of the first gate structures.
Chih-Kai Kang, Sheng-Yuan Hsueh, Yi-Chung Sheng, Kuo-Yu Liao, Shu-Hung Yu, Hung-Hsu Lin, Hsiang-Hung Peng
Filed: 5 Aug 20
Utility
Semiconductor Device and Method for Fabricating the Same
18 Nov 20
A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a spacer around the gate structure; forming a first contact etch stop layer (CESL) around the spacer; forming a mask layer on the first CESL; removing part of the mask layer; removing part of the first CESL; forming a second CESL on the mask layer and the gate structure; and removing part of the second CESL.
Te-Chang Hsu, Chun-Chia Chen, Yao-Jhan Wang, Chun-Jen Huang
Filed: 4 Aug 20
Utility
Method of forming semiconductor memory device with bit line contact structure
16 Nov 20
The present invention provides a method of forming a semiconductor device.
Feng-Yi Chang, Shih-Fang Tzou, Yu-Cheng Tung, Fu-Che Lee, Ming-Feng Kuo
Filed: 11 Nov 18
Utility
Resistor for dynamic random access memory
16 Nov 20
A resistor for dynamic random access memory includes a substrate with a memory cell region and a peripheral region defined thereon, and a resistor formed on a shallow trench isolation of the substrate, wherein the resistor is provided with a winding portion and terminal portions at two ends of the winding portion.
Yukihiro Nagai
Filed: 25 Feb 18
Utility
Semiconductor device and method for fabricating the same
16 Nov 20
A method for fabricating semiconductor device includes the steps of: forming an inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the IMD layer; forming a bottom electrode layer on the IMD layer, wherein the bottom electrode layer comprises a gradient concentration; forming a free layer on the bottom electrode layer; forming a top electrode layer on the free layer; and patterning the top electrode layer, the free layer, and the bottom electrode layer to form a magnetic tunneling junction (MTJ).
Hui-Lin Wang, Chia-Chang Hsu, Chen-Yi Weng, Chin-Yang Hsieh, Jing-Yin Jhang
Filed: 25 Nov 18
Utility
Semiconductor device and method for fabricating the same
16 Nov 20
A method for fabricating semiconductor device includes the steps of first providing a substrate having a magnetic tunnel junction (MTJ) region and an edge region, forming an first inter-metal dielectric (IMD) layer on the substrate, and then forming a first MTJ and a second MTJ on the first IMD layer, in which the first MTJ is disposed on the MTJ region while the second MTJ is disposed on the edge region.
Ching-Wen Hung, Yu-Ping Wang
Filed: 3 Jun 18
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