613 patents
Page 10 of 31
Utility
Manufacturing method for trench
29 Jun 20
Exemplary metal line structure and manufacturing method for a trench are provided.
Shin-Chi Chen, Jiunn-Hsiung Liao, Yu-Tsung Lai
Filed: 12 Dec 18
Utility
Semiconductor device with high-resistance gate
29 Jun 20
A semiconductor device and a manufacturing method thereof are provided.
Wei-Chang Liu, Zhen Chen, Shen-De Wang, Wang Xiang, Wei Ta, Ling-Gang Fang, Shang Xue
Filed: 28 Aug 18
Utility
Method for forming semiconductor pattern
29 Jun 20
The present invention provides a method for forming a semiconductor pattern, comprising: firstly, a target layer is provided and a first material layer is formed on the target layer, and then a first pattern is formed on the first material layer, followed by a first self-aligned double pattering step is performed, a plurality of first grooves are formed in the first material layer.
Gang-Yi Lin, Shih-Fang Tzou, Fu-Che Lee, Feng-Yi Chang, Ying-Chih Lin, Kai-Lou Huang, Yi-Ching Chang
Filed: 26 Jan 19
Utility
Magnetoresistive random access memory wherein number of memory cells in each string is equal to number of strings connected in parallel
29 Jun 20
A magnetic random access memory (MRAM) includes device strings coupled in parallel, each comprising magnetic tunnel junctions (MTJs) coupled in serial, wherein a quantity of the MTJs of each of the device strings is equal to a quantity of the device strings, and an equivalent resistance (Req) of the MTJs is equal to an average of the sum of a high resistance of one of the MTJs and a low resistance of another MTJ.
Ting-Hsiang Huang, Yi-Chung Sheng, Sheng-Yuan Hsueh, Kuo-Hsing Lee, Chih-Kai Kang
Filed: 21 Oct 18
Utility
Semiconductor device including conductive structure and manufacturing method thereof
29 Jun 20
A manufacturing method of a semiconductor device includes the following steps.
Te-Chang Hsu, Che-Hsien Lin, Cheng-Yeh Huang, Chun-Jen Huang, Yu-Chih Su, Yao-Jhan Wang
Filed: 17 Nov 18
Utility
Semiconductor device and method for forming the same
29 Jun 20
A semiconductor device is disclosed.
Kuang-Hsiu Chen, Sung-Yuan Tsai, Chi-Hsuan Tang, Kai-Hsiang Wang, Chao-Nan Chen, Shi-You Liu, Chun-Wei Yu, Yu-Ren Wang
Filed: 27 Oct 18
Utility
Manufacturing Method for Semiconductor Pattern
24 Jun 20
The present invention provides a method of fabricating a semiconductor pattern.
Chia-Hung Wang, En-Chiuan Liou, Chien-Hao Chen, Jhao-Hao Lee, Sho-Shen Lee, Chih-Yu Chiang
Filed: 9 Jan 19
Utility
Semiconductor Structure and Manufacturing Method Thereof
24 Jun 20
A semiconductor structure including a substrate, a CMOS device and a BJT is provided.
PURAKH RAJ VERMA, Kuo-Yuh Yang
Filed: 2 Mar 20
Utility
Semiconductor Device and Method for Fabricating the Same
24 Jun 20
A method for fabricating semiconductor device includes the steps of: providing a substrate having a fin-shaped structure thereon; forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion; forming a first gate structure on the SDB structure; forming an interlayer dielectric (ILD) layer around the first gate structure; transforming the first gate structure into a first metal gate; removing the first metal gate to form a first recess; and forming a dielectric layer in the first recess.
Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chi-Ting Wu, Chin-Hung Chen, Yu-Hsiang Lin
Filed: 1 Mar 20
Utility
Semiconductor Structure and Manufacturing Method Thereof
24 Jun 20
A semiconductor structure including a substrate, a complementary metal oxide semiconductor (CMOS) device, a bipolar junction transistor (BJT), and a first protection layer is provided.
Purakh Raj Verma, Kuo-Yuh Yang
Filed: 2 Mar 20
Utility
Semiconductor Device and Method of Manufacturing the Same
24 Jun 20
A semiconductor device is provided in the disclosure, including a substrate, multiple parallel fins protruding from the substrate and isolated by trenches, and a device insulating layer on the trenches between two fins, wherein the trench is provided with a central first trench and two second trenches at both sides of the first trench, and a depth of the first trench is deeper than a depth of the second trench, and the device insulating layer is provided with a top plane, a first trench and a second trench, and the fins protrude from the top plane, and the bottom surface of the second trench is lower than the bottom surface of the first trench.
Chih-Yi Wang, Tien-Shan Hsu, Cheng-Pu Chiu, Yao-Jhan Wang
Filed: 16 Jan 19
Utility
Semiconductor Device and Method for Fabricating the Same
24 Jun 20
A semiconductor device includes: a dummy gate on a substrate; a first control gate on one side of the dummy gate and a second control gate on another side of the dummy gate; a well in the substrate, wherein the well comprises a first conductive type; a first source/drain region between the dummy gate and the first control gate, wherein the first source/drain region comprises a second conductive type; a second source/drain region between the dummy gate and the second control gate, wherein the second source/drain region comprises the second conductive type; and a doped region directly under the dummy gate, wherein the doped region comprises the first conductive type.
Ting-Hsiang Huang, Yi-Chung Sheng, Sheng-Yuan Hsueh, Kuo-Hsing Lee, Chih-Kai Kang
Filed: 28 Jan 19
Utility
Semiconductor Device
24 Jun 20
A semiconductor device includes: a fin-shaped structure on the substrate; a shallow trench isolation (STI) around the fin-shaped structure; a single diffusion break (SDB) structure in the fin-shaped structure for dividing the fin-shaped structure into a first portion and a second portion; a first gate structure on the fin-shaped structure; a second gate structure on the STI; and a third gate structure on the SDB structure, wherein a width of the third gate structure is greater than a width of the second gate structure.
Cheng-Han Wu, Hsin-Yu Chen, Chun-Hao Lin, Shou-Wei Hsieh, Chih-Ming Su, Yi-Ren Chen, Yuan-Ting Chuang
Filed: 20 Jan 19
Utility
Semiconductor device and method to fabricate the semiconductor device
22 Jun 20
A structure of semiconductor device includes a substrate, having a dielectric layer on top.
Da-Jun Lin, Bin-Siang Tsai, Chich-Neng Chang
Filed: 5 Dec 18
Utility
Semiconductor device
22 Jun 20
A semiconductor device includes: a substrate having a first region and a second region; a first fin-shaped structure on the first region and a second fin-shaped structure on the second region, wherein each of the first fin-shaped structure and the second fin-shaped structure comprises a top portion and a bottom portion; a first doped layer around the bottom portion of the first fin-shaped structure; a second doped layer around the bottom portion of the second fin-shaped structure; a first liner on the first doped layer; and a second liner on the second doped layer.
Li-Wei Feng, Shih-Hung Tsai, Chao-Hung Lin, Hon-Huei Liu, Shih-Fang Hong, Jyh-Shyang Jenq
Filed: 1 Aug 18
Utility
Method for protecting epitaxial layer by forming a buffer layer on NMOS region
22 Jun 20
A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first gate structure on the first region and a second gate structure on the second region; forming a first spacer around the first gate structure; forming a first epitaxial layer adjacent to two sides of the first spacer; forming a buffer layer on the first gate structure; and forming a contact etch stop layer (CESL) on the buffer layer on the first region and the second gate structure on the second region.
Chun-Hao Lin, Hsin-Yu Chen, Shou-Wei Hsieh
Filed: 19 Feb 19
Utility
Semiconductor pattern for monitoring overlay and critical dimension at post-etching stage and metrology method of the same
22 Jun 20
A semiconductor pattern for monitoring overlay and critical dimension at post-etching stage is provided in the present invention, which include a first inverted-T shaped pattern with a base portion and a middle portion extending from the base portion and a second pattern adjacent and spaced apart from the base portion of the first inverted-T shaped pattern, wherein the first inverted-T shaped pattern and the second pattern are composed of a plurality of spacer patterns spaced apart from each other.
Chien-Hao Chen, Chien-Wei Huang, Chia-Hung Wang, Sho-Shen Lee
Filed: 7 Aug 18
Utility
Memory structure
22 Jun 20
A memory structure including a substrate, at least one stacked gate structure, a first spacer conductive layer, and a first contact is provided.
Wang Xiang, Chia-Ching Hsu, Chun-Sung Huang, Yung-Lin Tseng, Wei-Chang Liu, Shen-De Wang
Filed: 31 Oct 18
Utility
Semiconductor device and method for fabricating the same
22 Jun 20
A semiconductor device includes: a dummy gate on a substrate; a first control gate on one side of the dummy gate and a second control gate on another side of the dummy gate; a well in the substrate, wherein the well comprises a first conductive type; a first source/drain region between the dummy gate and the first control gate, wherein the first source/drain region comprises a second conductive type; a second source/drain region between the dummy gate and the second control gate, wherein the second source/drain region comprises the second conductive type; and a doped region directly under the dummy gate, wherein the doped region comprises the first conductive type.
Ting-Hsiang Huang, Yi-Chung Sheng, Sheng-Yuan Hsueh, Kuo-Hsing Lee, Chih-Kai Kang
Filed: 28 Jan 19
Utility
Testkey Detection Circuit
17 Jun 20
The invention provides a testkey detection circuit, including a plurality of oscillators and a driving circuit.
KUN-YUAN WU, Wei-Jen Wang, Chien-Fu Chen, Chen-Hsien Hsu, Yuan-Hui Chen, Ruei-Yau Chen, Cheng-Tsung Ku, Zhi-Hong Huang, Cheng-Yang Tsai, Yu-Lin Chen
Filed: 15 Jan 19