613 patents
Page 11 of 31
Utility
Layout Pattern for Sram and Manufacturing Methods Thereof
17 Jun 20
The present invention provides a static random access memory (SRAM), the SRAM includes a substrate, a SRAM pattern disposed on the substrate, wherein the SRAM pattern at least includes a first gate structure, a second gate structure and a third gate structure, arranged along a first direction, wherein the second gate structure and the third gate structure are parallel to the first gate structure, and a gap is disposed between the second gate structure and the third gate structure, and wherein the first gate structure is composed of a first elongated structure, a second elongated structure and a curved structure disposed between the first elongated structure and the second elongated structure, and wherein the curved structure is aligned with the gap along a second direction, and an interconnection contact structure disposed between the first gate structure and the second gate structure, and arranged along the first direction.
Te-Chang Hsu, Cheng-Pu Chiu, Chun-Jen Huang, Cheng-Yeh Huang, Che-Hsien Lin, Yao-Jhan Wang
Filed: 11 Dec 18
Utility
Semiconductor Structure with an Epitaxial Layer and Method of Manufacturing the Same
17 Jun 20
The present invention discloses a semiconductor structure with an epitaxial layer and method of manufacturing the same.
Hsiao-Pang Chou, Hon-Huei Liu, Ming-Chang Lu, Chin-Fu Lin, Yu-Cheng Tung
Filed: 7 Jan 19
Utility
Metal Interconnection and Forming Method Thereof
17 Jun 20
A metal interconnection includes a substrate, a first dielectric layer, metal wirings, air gaps and air gap dummies.
Chih-Yu Wu, Sheng-Yuan Hsueh, Kuo-Hsing Lee, Guan-Kai Huang
Filed: 11 Dec 18
Utility
Method for Forming a Semiconductor Structure
17 Jun 20
A method for forming a semiconductor structure is provided.
Hao-Yeh Liu, Jia-Feng Fang, Yu-Hsiang Lin, Ching-Hsiang Chiu, Chia-Wei Liu
Filed: 16 Dec 18
Utility
Semiconductor Device and Method for Fabricating the Same
17 Jun 20
A method for fabricating semiconductor device includes the steps of first providing a substrate having a fin-shaped structure thereon, forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion, and then forming more than one gate structures such as a first gate structure and a second gate structure on the SDB structure.
Fu-Jung Chuang, Po-Jen Chuang, Yu-Ren Wang, Chi-Mao Hsu, Chia-Ming Kuo, Guan-Wei Huang, Chun-Hsien Lin
Filed: 25 Feb 20
Utility
Semiconductor Device with Reduced Floating Body Effects and Fabrication Method Thereof
17 Jun 20
An SOI semiconductor device includes a substrate, a buried oxide layer disposed on the substrate, a top semiconductor layer disposed on the buried oxide layer, a source doping region and a drain doping region in the top semiconductor layer, a channel region between the source doping region and the drain doping region in the top semiconductor layer, a gate electrode on the channel region, and an embedded doping region disposed in the top semiconductor layer and directly under the channel region.
HAI BIAO YAO, Su Xing
Filed: 17 Dec 18
Utility
Fin Field Effect Transistor Structure with Particular Gate Appearance
17 Jun 20
A fin field effect transistor structure with particular gate appearance is provided in this disclosure, featuring a fin on a substrate and a gate on the substrate and traversing over the fin, wherein the fin is divided into an upper portion on a top surface of the fin and a lower portion on two sides of the fin, and the lower portion of the gate has protrusions laterally protruding in said first direction at positions abutting to the fin.
Chih-Yi Wang, Cheng-Pu Chiu, Huang-Ren Wei, Tien-Shan Hsu, Chi-Sheng Tseng, Yao-Jhan Wang
Filed: 7 Jan 19
Utility
Method of fabricating contact hole
15 Jun 20
A method of fabricating a contact hole includes the steps of providing a conductive line, a mask layer covering and contacting the conductive line, a high-k dielectric layer covering and contacting the mask layer, and a first silicon oxide layer covering and contacting the high-k dielectric layer, wherein the high-k dielectric layer includes a first metal oxide layer, a second metal oxide layer and a third metal oxide layer stacked from bottom to top.
Feng-Yi Chang, Shih-Fang Tzou, Fu-Che Lee, Hsin-Yu Chiang, Yu-Ching Chen
Filed: 27 Aug 19
Utility
Method for forming semiconductor structure
15 Jun 20
The present invention provides a method for fabricating a semiconductor structure.
Feng-Yi Chang, Fu-Che Lee
Filed: 7 May 18
Utility
Semiconductor structure with through silicon via and method for fabricating and testing the same
15 Jun 20
A semiconductor structure with a through silicon via includes a substrate having a front side and a back side.
Hsueh-Hao Shih
Filed: 19 May 19
Utility
Semiconductor structure for preventing row hammering issue in DRAM cell and method for manufacturing the same
15 Jun 20
A semiconductor structure for preventing row hammering issue in DRAM cell is provided in the present invention.
Chih-Chieh Tsai, Pin-Hong Chen, Tzu-Chieh Chen, Tsun-Min Cheng, Yi-Wei Chen, Hsin-Fu Huang, Chi-Mao Hsu, Shih-Fang Tzou
Filed: 4 Jul 18
Utility
Semiconductor device integrated with memory device and fabrication method thereof
15 Jun 20
A semiconductor device integrated with memory device includes a substrate, having a first side and a second side.
Zhi-Biao Zhou
Filed: 28 Feb 18
Utility
Fin field effect transistor structure with particular gate appearance
15 Jun 20
A fin field effect transistor structure with particular gate appearance is provided in this disclosure, featuring a fin on a substrate and a gate on the substrate and traversing over the fin, wherein the fin is divided into an upper portion on a top surface of the fin and a lower portion on two sides of the fin, and the lower portion of the gate has protrusions laterally protruding in said first direction at positions abutting to the fin.
Chih-Yi Wang, Cheng-Pu Chiu, Huang-Ren Wei, Tien-Shan Hsu, Chi-Sheng Tseng, Yao-Jhan Wang
Filed: 7 Jan 19
Utility
Semiconductor Device and Method to Fabricate the Semiconductor Device
10 Jun 20
A structure of semiconductor device includes a substrate, having a dielectric layer on top.
Da-Jun Lin, Bin-Siang Tsai, Chich-Neng Chang
Filed: 5 Dec 18
Utility
Semiconductor Device and Method to Fabricate the Semiconductor Device
10 Jun 20
A structure of semiconductor device includes a substrate, having a dielectric layer on top.
Da-Jun Lin, Bin-Siang Tsai, San-Fu Lin
Filed: 5 Dec 18
Utility
Semiconductor Structure
10 Jun 20
Provided is a semiconductor structure including a substrate, a doping layer, and a dielectric layer.
EN-CHIUAN LIOU, Yu-Cheng Tung
Filed: 13 Feb 20
Utility
Manufacturing Method of Semiconductor Memory Device
10 Jun 20
A manufacturing method of a semiconductor memory device includes the following steps.
Li-Wei Feng, Yu-Cheng Tung
Filed: 12 Feb 20
Utility
Semiconductor Memory Device and Fabrication Method Thereof
10 Jun 20
A method for fabricating a semiconductor memory device is disclosed.
Wen-Jen Wang, Chun-Hung Cheng, Chuan-Fu Wang
Filed: 16 Feb 20
Utility
Semiconductor Device and Method of Forming the Same
10 Jun 20
A semiconductor device includes a substrate having at least a trench formed therein.
Chia-Wei Wu, Ting-Pang Chung, Tien-Chen Chan, Shu-Yen Chan
Filed: 16 Feb 20
Utility
Fin Field Effect Transistor Having Crystalline Titanium Germanosilicide Stressor Layer
10 Jun 20
A semiconductor structure includes a semiconductor substrate, at least a silicon germanium (SiGe) epitaxial region disposed in the semiconductor substrate, and a contact structure disposed on the SiGe epitaxial region.
Cheng-Yeh Huang, Te-Chang Hsu, Chun-Jen Huang, Che-Hsien Lin, Yao-Jhan Wang
Filed: 13 Feb 20