613 patents
Page 13 of 31
Utility
Semiconductor memory device including gate structure
25 May 20
A semiconductor memory device includes a semiconductor substrate, a gate structure, a first spacer structure, and a gate connection structure.
Li-Wei Feng, Ying-Chiao Wang, Shih-Fang Tzou
Filed: 15 Jul 18
Utility
Semiconductor structure and method for forming the same
25 May 20
A semiconductor structure and a method for forming the same are provided.
Shin-Hung Li
Filed: 9 Apr 18
Utility
Gate-controlled bipolar junction transistor and operation method thereof
25 May 20
A gate-controlled bipolar junction transistor includes a substrate, an emitter region, a base region disposed on one side of the emitter region, and a collector region disposed on one side of the base region and being opposite to the emitter region.
Chen-Wei Pan, Sheng Cho
Filed: 16 Oct 18
Utility
Semiconductor device and method for fabricating the same
25 May 20
A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the MTJ, and a second spacer on another side of the MTJ, wherein the first spacer and the second spacer are asymmetric.
Yu-Chun Chen, Ya-Sheng Feng, Chiu-Jung Chiu, Hung-Chan Lin
Filed: 31 Oct 18
Utility
Automatic inline detection and wafer disposition system and method for automatic inline detection and wafer disposition
18 May 20
A method for automatic inline detection and wafer disposition includes the following steps.
Ching-Pei Lin, Chuang-Tse Wang, Fa-Fu Hu
Filed: 16 Dec 17
Utility
Method for fabricating a semiconductor structure on a semiconductor wafer
18 May 20
A method for fabricating a semiconductor structure on a semiconductor wafer is disclosed.
Feng-Yi Chang, Fu-Che Lee, Chieh-Te Chen, Ching-Pin Hsu
Filed: 17 Jul 18
Utility
Patterning method utilizing dummy mandrel
18 May 20
A method of forming a capacitor mask includes the following steps.
Feng-Yi Chang, Fu-Che Lee, Ying-Chih Lin, Gang-Yi Lin
Filed: 30 Jun 18
Utility
Interconnect structure
18 May 20
An interconnect layout structure, having a plurality of air gaps, includes a substrate having an insulating material disposed thereon and a conductive line disposed in the insulating material and extending along a first direction.
Tong-Yu Chen, Chia-Fang Lin
Filed: 21 Aug 18
Utility
Method of fabricating integrated circuit
18 May 20
A method of fabricating an integrated circuit includes the following steps.
Chung-Liang Chu, Yu-Ruei Chen, Yu-Hsiang Lin
Filed: 11 Dec 17
Utility
Semiconductor device and method of manufacturing the same
18 May 20
A semiconductor device and method of manufacturing the same is provided in the present invention.
Li-Wei Feng, Shih-Fang Tzou, Chien-Cheng Tsai, Chih-Chi Cheng, Chia-Wei Wu, Ger-Pin Lin
Filed: 1 Aug 18
Utility
Semiconductor device and method for fabricating the same
18 May 20
A method for fabricating semiconductor device includes the steps of: providing a material layer having a contact pad therein; forming a dielectric layer on the material layer and the contact pad; forming a doped oxide layer on the dielectric layer; forming an oxide layer on the doped oxide layer; performing a first etching process to remove part of the oxide layer, part of the doped oxide layer, and part of the dielectric layer to form a first contact hole; performing a second etching process to remove part of the doped oxide layer to form a second contact hole; and forming a conductive layer in the second contact hole to form a contact plug.
Chia-Liang Liao, Feng-Yi Chang, Fu-Che Lee, Chieh-Te Chen, Yi-Wang Zhan
Filed: 13 Mar 18
Utility
Dynamic random access memory
18 May 20
A dynamic random access memory (DRAM) includes a first bit line extending along a first direction, a first buried word line extending along a second direction, and an active region overlapping part of the first bit line and part of the first buried word line.
Wan-Chi Wu, Kai-Ping Chen, Hong-Ru Liu
Filed: 19 Dec 17
Utility
Semiconductor device and method for fabricating the same
18 May 20
A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region and a periphery region; forming a first trench and a second trench in substrate on the memory region, wherein a width of the second trench is greater than a width of the first trench; forming a first liner in the first trench and the second trench; forming a second liner on the first liner, wherein the second liner completely fills the first trench and partly fills the second trench; and planarizing the second liner and the first liner to form a first isolation structure and a second isolation structure.
Kun-Hsin Chen, Hsuan-Tung Chu, Tsuo-Wen Lu, Po-Chun Chen
Filed: 3 Jul 18
Utility
Low power crystal oscillator
18 May 20
A crystal oscillator with a configuration that allows for reduction of power consumption includes a crystal element, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a crystal element.
Ke-Han Chen, Min-Chia Wang
Filed: 23 May 19
Utility
Semiconductor structure and method of forming the same
18 May 20
A method of forming a semiconductor structure is disclosed.
I-Ming Tseng, Chun-Hsien Lin, Wen-An Liang
Filed: 4 Jul 18
Utility
Manufacturing Method of Semiconductor Memory Device
13 May 20
A semiconductor memory device includes a semiconductor substrate, bit line structures, storage node contacts, and isolation structures.
Yukihiro Nagai
Filed: 1 Jan 20
Utility
Method of Forming Fin Forced Stack Inverter
13 May 20
A method of forming a fin forced stack inverter includes the following steps.
Kuo-Hsing Lee, Yi-Chung Sheng, Sheng-Yuan Hsueh, Chih-Kai Kang
Filed: 12 Jan 20
Utility
Semiconductor device and method for fabricating the same
11 May 20
A method for fabricating semiconductor device includes the steps of: forming a titanium nitride (TiN) layer on a silicon layer; performing a first treatment process by reacting the TiN layer with dichlorosilane (DCS) to form a titanium silicon nitride (TiSiN) layer; forming a conductive layer on the TiSiN layer; and patterning the conductive layer, the metal silicon nitride layer, and the silicon layer to form a gate structure.
Tzu-Hao Liu, Yi-Wei Chen, Tsun-Min Cheng, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Po-Chih Wu, Pin-Hong Chen, Chun-Chieh Chiu, Tzu-Chieh Chen, Chih-Chien Liu, Chih-Chieh Tsai, Ji-Min Lin
Filed: 21 May 18
Utility
FinFET structure and fabricating method of gate structure
11 May 20
A method of forming a gate structure on a fin structure includes the steps of providing a fin structure covered by a first silicon oxide layer, a silicon nitride layer, a gate material and a cap material in sequence, wherein the silicon nitride layer contacts the first silicon oxide layer.
Yi-Liang Ye, Kuang-Hsiu Chen, Chun-Wei Yu, Chueh-Yang Liu, Yu-Ren Wang
Filed: 13 May 19
Utility
Manufacturing method of semiconductor device
11 May 20
A manufacturing method of a semiconductor device includes: providing a substrate having memory and high voltage regions; sequentially forming a floating gate layer and a hard mask layer on the substrate; patterning the hard mask layer to form a first opening exposing a portion of the floating gate layer in the range of the memory region; patterning the hard mask layer and the floating gate layer to form a second opening overlapped with the high voltage region; performing a first thermal growth process to simultaneously form a first oxide structure on the portion of the floating gate layer exposed by the first opening, and to form a second oxide structure on a portion of the substrate overlapped with the second opening; removing the hard mask layer; and patterning the floating gate layer by using the first oxide structure as a mask.
Jianjun Yang, Cheng-Hua Yang, Fan-Chi Meng, Chih-Chien Chang, Shen-De Wang
Filed: 13 Dec 18