613 patents
Page 3 of 31
Utility
Semiconductor Device and Method for Fabricating the Same
14 Oct 20
A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the fin-shaped structure into a first portion and a second portion, and a gate structure on the SDB structure.
Fu-Jung Chuang, Ching-Ling Lin, Po-Jen Chuang, Yu-Ren Wang, Wen-An Liang, Chia-Ming Kuo, Guan-Wei Huang, Yuan-Yu Chung, I-Ming Tseng
Filed: 28 Jun 20
Utility
High Electron Mobility Transistor
14 Oct 20
A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer; forming a patterned mask on the first barrier layer; forming a second barrier layer adjacent to two sides of the patterned mask; removing the patterned mask to form a recess; forming a gate electrode in the recess; and forming a source electrode and a drain electrode adjacent to two sides of the gate electrode.
Po-Yu Yang
Filed: 12 May 19
Utility
Semiconductor Device
14 Oct 20
A semiconductor device includes a buried dielectric layer, a first gate structure, a second gate structure, a first source/drain region, a second source/drain region, a first contact structure and a second contact structure.
Purakh Raj Verma, Ching-Yang Wen, Li Wang, Kai Cheng
Filed: 8 May 19
Utility
Method for fabricating a semiconductor device
12 Oct 20
A method for fabricating a semiconductor device includes the steps of: providing a first dielectric layer having a metal layer therein; forming a second dielectric layer on the first dielectric layer and the metal layer; forming a metal oxide layer on the second dielectric layer; performing a first etching process by using a chlorine-based etchant to remove part of the metal oxide layer to forma via opening and expose the second dielectric layer; forming a block layer on sidewalls of the metal oxide layer and a top surface of the second dielectric layer; and performing a second etching process by using a fluorine-based etchant to remove part of the block layer and part of the second dielectric layer for exposing a top surface of the metal layer.
Chih-Wei Kuo, Yu-Tsung Lai, Jiunn-Hsiung Liao
Filed: 21 Sep 17
Utility
Semiconductor device and method for fabricating the same
12 Oct 20
A method for fabricating semiconductor device includes the steps of first forming a silicon layer on a substrate and then forming a metal silicon nitride layer on the silicon layer, in which the metal silicon nitride layer includes a bottom portion, a middle portion, and a top portion and a concentration of silicon in the top portion is greater than a concentration of silicon in the middle portion.
Chun-Chieh Chiu, Pin-Hong Chen, Yi-Wei Chen, Tsun-Min Cheng, Chih-Chien Liu, Tzu-Chieh Chen, Chih-Chieh Tsai, Kai-Jiun Chang, Yi-An Huang, Chia-Chen Wu, Tzu-Hao Liu
Filed: 21 May 18
Utility
Photodetector and method for fabricating the same
12 Oct 20
A photodetector includes a substrate, at least one nanowire and a cladding layer.
Guo-Zhong Xing, Cheng-Yu Hsieh, Chien-En Hsu
Filed: 24 Feb 19
Utility
Manufacturing method of memory device
12 Oct 20
A method for manufacturing a memory device is provided, the method includes the following steps: firstly, providing a dielectric layer, then simultaneously forming a contact window and an alignment mark trench in the dielectric layer, wherein the contact window exposes a lower metal line, then forming a conductive layer on the surface of the dielectric layer, in the contact window and in the alignment mark trench, performing a planarization step on the conductive layer, and leaving a residue in the alignment mark trench.
Hsin-Jung Liu, Kun-Ju Li, Ang Chan, Chau-Chung Hou, Yu-Lung Shih
Filed: 21 Jul 19
Utility
Self-biased amplifier for use with a low-power crystal oscillator
12 Oct 20
A self-biased amplifier includes a capacitor, a bias generation circuit and a common source amplifier.
Ke-Han Chen, Min-Chia Wang
Filed: 27 Dec 18
Utility
Semiconductor Device and Method for Fabricating the Same
7 Oct 20
A semiconductor device includes a substrate having a first region and a second region and a gate structure on the first region and the second region of the substrate.
Yi-Fan Li, Wen-Yen Huang, Shih-Min Chou, Zhen Wu, Nien-Ting Ho, Chih-Chiang Wu, Ti-Bin Chen
Filed: 20 Jun 20
Utility
Microelectromechanical system structure and method for fabricating the same
5 Oct 20
A microelectromechanical system structure and a method for fabricating the same are provided.
Chang-Sheng Hsu, Chih-Fan Hu, Chia-Wei Lee, En Chan Chen, Shih-Wei Li
Filed: 20 Aug 18
Utility
Manufacturing method of semiconductor structure
5 Oct 20
A manufacturing method of a semiconductor structure includes the following steps.
Yi-Liang Ye, Chun-Wei Yu, Yu-Ren Wang, Shi-You Liu, Shao-Hua Hsu
Filed: 5 Nov 18
Utility
Transistor structure
5 Oct 20
A transistor structure includes a source region and a drain region disposed in a substrate, extending along a first direction.
Shih-Yin Hsiao, Ching-Chung Yang, Kuan-Liang Liu
Filed: 30 May 19
Utility
Method of designing a layout of a static random access memory pattern
5 Oct 20
The present invention provides a method of designing a layout of a static random access memory (SRAM) pattern, the method includes the following steps: firstly, a target pattern is provided, and according to the target pattern, a plurality of first patterns and a first dummy pattern are formed in a substrate, the first pattern that disposed at the outermost boundary of the first patterns is defined as a first edge pattern, and the first dummy pattern is disposed adjacent to the first edge pattern, next, the first dummy pattern is removed, and afterwards, according to the target pattern, a plurality of second patterns are formed in the substrate, the second patterns comprises a second edge pattern that is disposed between the first edge pattern and an original position of the first dummy pattern.
Yu-Chang Lin, Wei-Cyuan Lo, Yung-Feng Cheng
Filed: 26 Dec 18
Utility
Semiconductor structure and manufacturing method thereof
5 Oct 20
A semiconductor structure and a manufacturing method thereof are provided, wherein the semiconductor structure includes a substrate and gate structures.
Zhenhai Zhang
Filed: 28 Jun 17
Utility
Semiconductor device and method for fabricating the same
5 Oct 20
A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a polymer block on a corner between the gate structure and the substrate; performing an oxidation process to form a first seal layer on sidewalls of the gate structure; and forming a source/drain region adjacent to two sides of the gate structure.
Fu-Jung Chuang, Tsuo-Wen Lu, Chia-Ming Kuo, Po-Jen Chuang, Chi-Mao Hsu
Filed: 3 Jul 19
Utility
Magnetoresistive memory cell and method for fabricating the same
5 Oct 20
A magnetoresistive memory cell is provided including a substrate.
Ya-Sheng Feng, Yu-Chun Chen, Chiu-Jung Chiu, Hung-Chan Lin
Filed: 30 Sep 18
Utility
Method of forming layout definition of semiconductor device
5 Oct 20
A method of forming a layout definition of a semiconductor device includes the following steps.
Wei-Lun Hsu, Gang-Yi Lin, Yu-Hsiang Hung, Ying-Chih Lin, Feng-Yi Chang, Ming-Te Wei, Shih-Fang Tzou, Fu-Che Lee, Chia-Liang Liao
Filed: 30 Oct 18
Utility
Static random access memory cell and operating method thereof capable of reducing leakage current
5 Oct 20
A static random access memory cell includes first and second cross-coupled inverters, a write transistor and a read transistor.
Yung-Ting Chen, Hsueh-Chun Hsiao
Filed: 2 Mar 19
Utility
Semiconductor Device and Method for Fabricating the Same
30 Sep 20
A method for fabricating semiconductor device includes: forming a fin-shaped structure on a substrate, wherein the fin-shaped structure is extending along a first direction; forming a gate layer on the fin-shaped structure; removing part of the gate layer and part of the fin-shaped structure to form a first trench for dividing the fin-shaped structure into a first portion and a second portion, wherein the first trench is extending along a second direction; forming a patterned mask on the gate layer and into the first trench; removing part of the gate layer and part of the fin-shaped structure to form a second trench, wherein the second trench is extending along the first direction; and filling a dielectric layer in the first trench and the second trench.
Chun-Hao Lin, Hsin-Yu Chen, Shou-Wei Hsieh
Filed: 28 Apr 19
Utility
Method for evaluating stability of semiconductor manufacturing process
28 Sep 20
The present invention provides an overlay mark, including a substrate and plural sets of first pattern block and second pattern block.
En-Chiuan Liou, Yu-Cheng Tung
Filed: 27 Mar 19