613 patents
Page 5 of 31
Utility
Antifuse device and method of operating the same
7 Sep 20
An antifuse device is disclosed.
Tsai-Yu Huang, Pin-Yao Wang
Filed: 3 Jul 18
Utility
Semiconductor device including bit line structure of dynamic random access memory (DRAM) and method for fabricating the same
7 Sep 20
A method for fabricating semiconductor device includes the steps of: forming a bit line structure on a substrate; forming a first spacer, a second spacer, and a third spacer around the bit line structure; forming an interlayer dielectric (ILD) layer on the bit line structure; planarizing part of the ILD layer; removing the ILD layer and the second spacer to form a recess between the first spacer and the third spacer; and forming a liner in the recess.
Chih-Chien Liu, Chia-Lung Chang, Tzu-Chin Wu, Wei-Lun Hsu
Filed: 13 Feb 18
Utility
Memory structure and manufacturing method thereof
7 Sep 20
A memory structure including a substrate, a first gate structure, a second gate structure, a first spacer, a second spacer, and a third spacer is provided.
Hsueh-Chun Hsiao, Tzu-Yun Chang, Chuan-Fu Wang, Yu-Huang Yeh
Filed: 5 Sep 18
Utility
Manufacturing Method of Semiconductor Device
2 Sep 20
A manufacturing method of a semiconductor device includes the following steps.
Te-Chang Hsu, Che-Hsien Lin, Cheng-Yeh Huang, Chun-Jen Huang, Yu-Chih Su, Yao-Jhan Wang
Filed: 18 May 20
Utility
Mask weak pattern recognition apparatus and mask weak pattern recognition method
31 Aug 20
A mask weak pattern recognition apparatus and a mask weak pattern recognition method are provided.
Pin-Yen Tsai, Hsu-Tang Liu, Yi-Jung Chang, Chun-Liang Hou
Filed: 13 Feb 19
Utility
Static random access memory device with keeper circuit
31 Aug 20
An SRAM device includes a memory cell and a keeper circuit.
Chih-Wei Tsai, Tsan-Tang Chen, Chung-Cheng Tsai, Yen-Hsueh Huang, Chang-Ting Lo, Chun-Yen Tseng, Yu-Tse Kuo
Filed: 27 Jun 19
Utility
Semiconductor device including buried insulation layer and manufacturing method thereof
31 Aug 20
A semiconductor device includes a buried insulation layer, a semiconductor layer, a gate structure, a source doped region, and a drain doped region.
Purakh Raj Verma, Su Xing, Ching-Yang Wen
Filed: 21 Mar 18
Utility
Semiconductor device and method for fabricating the same
31 Aug 20
A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a plurality of fin shaped structures and an insulating layer.
En-Chiuan Liou, Yu-Cheng Tung
Filed: 21 Aug 18
Utility
Semiconductor device and method of manufacturing a semiconductor device
31 Aug 20
A semiconductor device includes a memory region, a plurality of bit lines in the memory region, a first low-k dielectric layer on each sidewall of each bit line, a plurality of storage node regions between the bit lines, and a second low-k dielectric layer surrounding each storage node region.
Chien-Ting Ho, Shih-Fang Tzou, Chun-Yuan Wu, Li-Wei Feng, Yu-Chieh Lin, Ying-Chiao Wang, Tsung-Ying Tsai
Filed: 10 Dec 18
Utility
Method for forming dynamic random access memory structure
31 Aug 20
The present invention provides a method for forming a dynamic random access memory (DRAM) structure, the method including: firstly, a substrate is provided, a cell region and a peripheral region are defined on the substrate, a plurality of buried word lines is then formed in the cell region of the substrate, next, a shallow trench isolation structure is formed in the peripheral region adjacent to the cell region, wherein a concave top surface is formed on the shallow trench isolation structure, afterwards, a first dummy bit line gate is formed within the shallow trench isolation structure of the peripheral area, and a second dummy bit line gate is formed in the cell region and adjacent to the first dummy bit line gate, wherein a top surface of the first dummy bit line gate is lower than a top surface of the second dummy bit line gate.
En-Chiuan Liou, Yu-Cheng Tung, Chih-Wei Yang, Sho-Shen Lee
Filed: 15 Sep 19
Utility
Semiconductor device
31 Aug 20
A semiconductor device includes a substrate, a first dielectric layer on the substrate, a hard mask layer on the first dielectric layer, a trench in the hard mask layer and the first dielectric layer, a first source/drain electrode layer on a sidewall of the trench, a second dielectric layer on the first source/drain electrode layer in the trench, a second source/drain electrode layer on the second dielectric layer in the trench, a third dielectric layer on the second source/drain electrode layer in the trench, an ILD layer overlying the trench, an nFET disposed over the trench, and a pFET disposed over the trench and spaced apart from the nFET.
Ching-Wen Hung
Filed: 23 Mar 20
Utility
Etching Back Method
26 Aug 20
A material layer having recesses is formed on a substrate including a high pattern density area and a low pattern density area.
Kuan-Ying Lai, Chang-Mao Wang, Hsin-Yu Hsieh
Filed: 25 Feb 19
Utility
Semiconductor Device
26 Aug 20
A semiconductor device includes: a substrate having a first region and a second region; a first fin-shaped structure on the first region and a second fin-shaped structure on the second region, wherein each of the first fin-shaped structure and the second fin-shaped structure comprises a top portion and a bottom portion; a first doped layer around the bottom portion of the first fin-shaped structure; a second doped layer around the bottom portion of the second fin-shaped structure; a first liner on the first doped layer; and a second liner on the second doped layer.
Li-Wei Feng, Shih-Hung Tsai, Chao-Hung Lin, Hon-Huei Liu, Shih-Fang Hong, Jyh-Shyang Jenq
Filed: 11 May 20
Utility
Semiconductor Memory Device and Manufacturing Method Thereof
26 Aug 20
A semiconductor memory device includes a semiconductor substrate, bit line structures, storage node contacts, isolation structures, a first spacer, a second spacer, and a third spacer.
Po-Han Wu, Feng-Yi Chang, Fu-Che Lee, Wen-Chieh Lu
Filed: 21 Mar 19
Utility
Method of fabricating semiconductor devices with same conductive type but different threshold voltages
24 Aug 20
A method of manufacturing semiconductor devices, including the steps of providing a substrate with a first active region, a second active region and a third active region, forming dummy gates in the first active region, the second active region and the third active region, removing the dummy gates to form trenches in the first active region, the second active region and the third active region, forming a high-k dielectric layer, a first bottom barrier metal layer on the high-k dielectric layer, a second bottom barrier metal layer on the first bottom barrier metal layer, and a first work function metal layer on the second bottom barrier metal layer in the trenches, removing the first work function metal layer from the second active region and the third active region, removing the second bottom barrier metal layer from the third region, and filling up each trench with a low resistance metal.
Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chin-Hung Chen, Chi-Ting Wu, Yu-Hsiang Lin
Filed: 10 Feb 19
Utility
Semiconductor structure and method for forming the same
24 Aug 20
A semiconductor structure is provided, the semiconductor structure includes a front oxide layer on a backside oxide layer, a front electronic component in the front oxide layer, a backside electronic component in the backside oxide layer, and a shield structure disposed between the front oxide layer and the backside oxide layer, the shield structure includes a patterned buried metal layer, two front contact structures disposed on a front surface of the patterned buried metal layer, and two back contact structures disposed on a backside of the patterned buried metal layer.
Zhibiao Zhou
Filed: 30 Mar 19
Utility
Storage node contact structure of a memory device and manufacturing methods thereof
24 Aug 20
The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).
Pin-Hong Chen, Tsun-Min Cheng, Chih-Chieh Tsai, Tzu-Chieh Chen, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Yi-Wei Chen, Hsin-Fu Huang, Chi-Mao Hsu, Li-Wei Feng, Ying-Chiao Wang, Chung-Yen Feng
Filed: 14 Mar 18
Utility
Integrated circuit device and method of fabricating integrated circuit
24 Aug 20
An integrated circuit device includes a complementary metal oxide semiconductor (CMOS) image sensor.
Kuo-Chih Lai, Shih-Min Chou, Ko-Wei Lin, Chin-Fu Lin, Wei-Chuan Tsai, Chun-Yao Yang, Chia-Fu Cheng, Yi-Syun Chou, Wei Chen
Filed: 9 Jan 19
Utility
Semiconductor device
24 Aug 20
A semiconductor device including a substrate having a fin structure surrounded by a trench isolation region; a trench disposed in the fin structure; an interlayer dielectric layer disposed on the substrate; a working gate striding over the fin structure and on the first side of the trench; a dummy gate striding over the fin structure and on the second side of the trench; a doped source region in the fin structure; and a doped drain region in the fin structure.
Zhi-Cheng Lee, Wei-Jen Chen, Kai-Lin Lee
Filed: 7 Mar 20
Utility
Mask Weak Pattern Recognition Apparatus and Mask Weak Pattern Recognition Method
19 Aug 20
A mask weak pattern recognition apparatus and a mask weak pattern recognition method are provided.
Pin-Yen TSAI, Hsu-Tang LIU, Yi-Jung CHANG, Chun-Liang HOU
Filed: 13 Feb 19