613 patents
Page 6 of 31
Utility
Metal-oxide-semiconductor Transistor and Method of Fabricating the Same
19 Aug 20
A metal-oxide-semiconductor (MOS) transistor includes a substrate.
HSIANG-HUA HSU, Liang-An Huang, Sheng-Chen Chung, Chen-An Kuo, Chiu-Te Lee, Chih-Chung Wang, Kuang-Hsiu Chen, Ke-Feng Lin, Yan-Huei Li, Kai-Ting Hu
Filed: 18 Mar 19
Utility
Method of Forming Gate
19 Aug 20
A method of forming gates includes the following steps.
Po-Tsang Chen, Wen-Liang Huang, Chun-Chi Yu
Filed: 14 Feb 19
Utility
Semiconductor Device
19 Aug 20
A structure of semiconductor device includes a substrate, having a dielectric layer on top.
Da-Jun Lin, Bin-Siang Tsai, Chich-Neng Chang
Filed: 3 May 20
Utility
Magnetoresistive Random Access Memory
19 Aug 20
A semiconductor device preferably includes a metal-oxide semiconductor (MOS) transistor disposed on a substrate, an interlayer dielectric (ILD) layer disposed on the MOS transistor, and a magnetic tunneling junction (MTJ) disposed on the ILD layer.
Hui-Lin Wang, Ying-Cheng Liu, Yi-An Shih, Yi-Hui Lee, Chen-Yi Weng, Chin-Yang Hsieh, I-Ming Tseng, Jing-Yin Jhang, Yu-Ping Wang
Filed: 9 Mar 19
Utility
Semiconductor Structure for Preventing Row Hammering Issue In Dram Cell and Method for Manufacturing the Same
19 Aug 20
A method of manufacturing a semiconductor device for preventing row hammering issue in DRAM cell, including the steps of providing a substrate, forming a trench in the substrate, forming a gate dielectric conformally on the trench, forming an n-type work function metal layer conformally on the substrate and the gate dielectric, forming a titanium nitride layer conformally on the n-type work function metal layer, and filling a buried word line in the trench.
Chih-Chieh Tsai, Pin-Hong Chen, Tzu-Chieh Chen, Tsun-Min Cheng, Yi-Wei Chen, Hsin-Fu Huang, Chi-Mao Hsu, Shih-Fang Tzou
Filed: 4 May 20
Utility
Photomask
17 Aug 20
The present invention provides a photomask, comprising: a substrate, a first region, a second region and a third region are defined thereon, wherein the third region is disposed between the first region and the second region, a patterned layer disposed on the substrate, wherein the patterned layer comprises a first patterned layer disposed in the first region, a second patterned layer disposed in the second region, and a third patterned layer disposed in the third region, and wherein a thickness of the first patterned layer is equal to a thickness of the second patterned layer, the thickness of the first patterned layer is different from a thickness of the third patterned layer, and at least one recess disposed in the third region.
Yen-Pu Chen, Shu-Yen Liu, Tang-Chun Weng, Tuan-Yen Yu
Filed: 21 May 18
Utility
Semiconductor Device and Method for Fabricating the Same
12 Aug 20
A semiconductor device includes a fin-shaped structure on a substrate, a gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the gate structure, and a single diffusion break (SDB) structure in the ILD layer and the fin-shaped structure.
Ching-Ling Lin, Wen-An Liang, Chen-Ming Huang
Filed: 26 Apr 20
Utility
Sram Structure
12 Aug 20
An SRAM structure includes a substrate.
Chien-Hui Huang, Tsung-Hsun Wu, Po-Lin Chen
Filed: 10 Mar 19
Utility
Static Random Access Memory Cell and Operating Method Thereof Capable of Reducing Leakage Current
12 Aug 20
A static random access memory cell includes first and second cross-coupled inverters, a write transistor and a read transistor.
Yung-Ting Chen, Hsueh-Chun Hsiao
Filed: 2 Mar 19
Utility
Interconnection Structure and Method of Forming the Same
12 Aug 20
A method of forming an interconnection structure is disclosed, including providing a substrate, forming a patterned layer on the substrate, the patterned layer comprising at least a trench formed therein, depositing a first dielectric layer on the patterned layer and sealing an air gap in the trench, depositing a second dielectric layer on the first dielectric layer and completely covering the patterned layer, and performing a curing process to the first dielectric layer and the second dielectric layer.
Yu-Cheng Lin, Chich-Neng Chang, Bin-Siang Tsai
Filed: 25 Apr 20
Utility
Bit Line Gate Structure of Dynamic Random Access Memory (Dram)
12 Aug 20
A method of forming a bit line gate structure of a dynamic random access memory (DRAM) includes the following steps.
Yi-Wei Chen, Pin-Hong Chen, Tsun-Min Cheng, Chun-Chieh Chiu
Filed: 26 Apr 20
Utility
Method for Correcting Mask Pattern and Mask Pattern Thereof
12 Aug 20
A method for correcting a mask pattern includes: providing an original mask pattern including at least one dense pattern area and at least one isolated pattern area, and the original mask pattern being divided into a first pattern and a second pattern, wherein the first pattern is formed in the isolated pattern area and extends to the dense pattern area, and the second pattern is formed in the dense pattern area; forming at least one slot on at least one section of the first pattern, and the at least one section of the first pattern is located on at least one transition area between the at least one isolated pattern area and the at least one dense pattern area; and performing an optical proximity correction operation on the first pattern formed with at least one slot and the second pattern.
Chia-Chen SUN, Yu-Cheng TUNG, Sheng-Yuan HSUEH, Fan Wei LIN
Filed: 10 Feb 19
Utility
Micro-electro-mechanical system structure and method for fabricating the same
10 Aug 20
A MEMS structure includes a substrate, a dielectric layer, a membrane, a backplate, and a blocking layer.
Yuan-Sheng Lin, Jung-Hao Chang, Chang-Sheng Hsu, Weng-Yi Chen
Filed: 24 Feb 19
Utility
Semiconductor device and method for fabricating the same
10 Aug 20
A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the fin-shaped structure into a first portion and a second portion, and a gate structure on the SDB structure.
Fu-Jung Chuang, Ching-Ling Lin, Po-Jen Chuang, Yu-Ren Wang, Wen-An Liang, Chia-Ming Kuo, Guan-Wei Huang, Yuan-Yu Chung, I-Ming Tseng
Filed: 4 Feb 20
Utility
Structure of Memory Cell and Method for Fabricating the Same
5 Aug 20
A structure of memory cell includes a memory gate structure, disposed on a substrate, wherein the substrate has an indent region aside the memory gate structure.
Chin-Chin Tsai
Filed: 30 Jan 19
Utility
High Electron Mobility Transistor
5 Aug 20
According to an embodiment of the present invention, a high electron mobility transistor (HEMT) includes: a buffer layer on a substrate; a carrier transit layer on the buffer layer; a carrier supply layer on the carrier transit layer; a gate electrode on the carrier supply layer; and a source and a drain adjacent to two sides of the gate electrode.
Huai-Tzu Chiang, Sheng-Hao Lin, Kuan-Hung Liu
Filed: 5 Mar 19
Utility
Method of Forming Semiconductor Device
5 Aug 20
The present invention relates to a semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure, an insulating stacked structure and a first conductive layer.
Wen-Wu Wan, Tien-Hsiang Cheng, Kun-Hsuan Chung
Filed: 20 Apr 20
Utility
Semiconductor Apparatus and Method for Manufacturing Semiconductor Apparatus
5 Aug 20
Semiconductor apparatus and method for manufacturing semiconductor apparatus are provided.
YU-JIE LIN
Filed: 5 Mar 19
Utility
Method of self-aligned double patterning
3 Aug 20
A method of self-aligned double patterning is disclosed in the present invention, which includes the step of forming multiple mandrels on a hard mask layer and spacers at two sides of each mandrel, forming a protection layer filling between the spacers, removing the mandrels to expose the hard mask layer, and performing an anisotropic etch process using the spacers and the protection layer as an etch mask to remove a portion of hard mask layer, so that a thickness of hard mask layer exposed between the spacers equals to a thickness of hard mask layer under the protection layer.
Feng-Yi Chang, Fu-Che Lee, Ying-Chih Lin, Gang-Yi Lin, Chieh-Te Chen, Yi-Ching Chang
Filed: 18 Sep 18
Utility
Planarization method
3 Aug 20
A planarization method is provided and includes the following steps.
Po-Cheng Huang, Yu-Ting Li, Fu-Shou Tsai, Wen-Chin Lin, Chun-Liang Liu
Filed: 3 Jan 18