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TSM Taiwan Semiconductor Manufacturing

APP
Utility
Packaging Method and Associated Packaging Structure
20 Jan 22
The present disclosure provides a packaging method, including: providing a first semiconductor substrate; forming a bonding region on the first semiconductor substrate, wherein the bonding region of the first semiconductor substrate includes a first bonding metal layer and a second bonding metal layer; providing a second semiconductor substrate having a bonding region, wherein the bonding region of the second semiconductor substrate includes a third bonding layer; and bonding the first semiconductor substrate to the second semiconductor substrate by bringing the bonding region of the first semiconductor substrate in contact with the bonding region of the second semiconductor substrate; wherein the first and third bonding metal layers include copper (Cu), and the second bonding metal layer includes Tin (Sn).
Chih-Ming CHEN, Yuan-Chih HSIEH, Chung-Yi YU
Filed: 2 Aug 21
APP
Utility
Spacer Structure for Semiconductor Device and Method for Forming the Same
20 Jan 22
The present disclosure describes a semiconductor structure and a method for forming the same.
Han-Yu LIN, Jhih-Rong Huang, Yen-Tien Tung, Tzer-Min Shen, Fu-Ting Yen, Gary Chan, Keng-Chu Lin, Li-Te Lin, Pinyen Lin
Filed: 7 Jan 21
APP
Utility
Composition and Method for Polishing and Integrated Circuit
20 Jan 22
A slurry composition, a polishing method and an integrated circuit are provided.
JI CUI, CHI-JEN LIU, CHIH-CHIEH CHANG, KAO-FENG LIAO, PENG-CHUNG JANGJIAN, CHUN-WEI HSU, TING-HSUN CHANG, LIANG-GUANG CHEN, KEI-WEI CHEN, HUI-CHI HUANG
Filed: 24 Nov 20
APP
Utility
Semiconductor Packages and Methods of Forming the Same
20 Jan 22
A semiconductor package includes a circuit board structure, a first redistribution layer structure and first bonding elements.
Jung-Wei Cheng, Jiun-Yi Wu, Hsin-Yu Pan, Tsung-Ding Wang, Yu-Min Liang, Wei-Yu Chen
Filed: 20 Jul 20
APP
Utility
Waveguide Structure and Method for Forming the Same
20 Jan 22
An optical attenuating structure is provided.
HUAN-NENG CHEN, FENG-WEI KUO, MIN-HSIANG HSU, LAN-CHOU CHO, CHEWN-PU JOU, WEN-SHIANG LIAO
Filed: 20 Jul 20
APP
Utility
Semiconductor Device and Method for Forming the Same
20 Jan 22
A semiconductor device includes a substrate, a semiconductor fin, a source/drain structure, a first buried power line, a contact, a first through substrate via (TSV), and a second TSV.
Marcus Johannes Henricus VAN DAL, Gerben DOORNBOS
Filed: 9 Mar 21
APP
Utility
In-memory Computation Circuit and Method
20 Jan 22
A memory circuit includes a selection circuit, a column of memory cells, and an adder tree.
Yu-Der CHIH, Hidehiro FUJIWARA, Yi-Chun SHIH, Po-Hao LEE, Yen-Huei CHEN, Chia-Fu LEE, Jonathan Tsung-Yung CHANG
Filed: 16 Mar 21
APP
Utility
Memory Device and Method for Fabricating the Same
20 Jan 22
A memory device including a word line, memory cells, source lines and bit lines is provided.
Han-Jong Chia, Meng-Han Lin, Yu-Ming Lin
Filed: 1 Feb 21
APP
Utility
Method of Operating an Integrated Circuit and Integrated Circuit
20 Jan 22
A method of operating an integrated circuit includes writing data to each memory cell in a first memory cell array, powering off the integrated circuit, powering on the integrated circuit, reading data from each memory cell in the first memory cell array in response to powering on the integrated circuit, and determining whether to allow an authentication operation of the integrated circuit in response to reading data from each memory cell in the first memory cell array.
Shih-Lien Linus LU
Filed: 30 Mar 21
APP
Utility
Multilayer Masking Layer and Method of Forming Same
20 Jan 22
A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.
Wen-Ju Chen, Chung-Ting Ko, Ya-Lan Chang, Ting-Gang Chen, Tai-Chun Huang, Chi On Chui
Filed: 10 Mar 21
APP
Utility
Radio Frequency Screen for an Ultraviolet Lamp System
20 Jan 22
A radio frequency (RF) screen for a microwave powered ultraviolet (UV) lamp system is disclosed.
Sheng-chun YANG, Po-Wei LIANG, Chao-Hung WAN, Yi-Ming LIN, Liu Che KANG
Filed: 15 Jul 20
APP
Utility
Semiconductor Device and Method of Forming the Same
20 Jan 22
A semiconductor device includes a storage element layer and a selector.
Georgios Vellianitis, Gerben Doornbos, Marcus Johannes Henricus Van Dal, Mauricio MANFRINI
Filed: 20 Jul 20
APP
Utility
Technique for Semiconductor Manufacturing
20 Jan 22
A technique for semiconductor manufacturing is provided.
HAN-YU LIN, LI-TE LIN, TZE-CHUNG LIN, FANG-WEI LEE, YI-LUN CHEN, JUNG-HAO CHANG, YI-CHEN LO, FO-JU LIN, KENICHI SANO, PINYEN LIN
Filed: 20 Jan 21
APP
Utility
System and Method for Supplying Chemical Solution
20 Jan 22
A system includes a chemical storage tank, a pipeline, a pump, a first electrostatic probe, and a control unit.
Chih-Chiang Tseng, Ming-Lee Lee, Chiang Jen Chen
Filed: 17 Jul 20
APP
Utility
Multi-Liner TSV Structure and Method Forming Same
20 Jan 22
A method includes etching a substrate to form an opening, depositing a first dielectric liner extending into the opening, and depositing a second dielectric liner over the first dielectric liner.
Ming-Fa Chen, Chin-Shyh Wang, Chao-Wen Shih
Filed: 28 Dec 20
APP
Utility
Eccentric Via Structures for Stress Reduction
20 Jan 22
A method includes forming a first dielectric layer, forming a first redistribution line including a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening.
Shu-Shen Yeh, Che-Chia Yang, Chia-Kuei Hsu, Po-Yao Lin, Shin-Puu Jeng, Chia-Hsiang Lin
Filed: 18 Dec 20
APP
Utility
Graphene-Assisted Low-Resistance Interconnect Structures and Methods of Formation Thereof
20 Jan 22
A semiconductor structure is provided.
Shin-Yi Yang, Yu-Chen Chan, Ming-Han Lee, Hai-Ching Chen, Shau-Lin Shue
Filed: 2 Aug 21
APP
Utility
Stacking Via Structures for Stress Reduction
20 Jan 22
A method includes forming a first dielectric layer, forming a first redistribution line comprising a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening.
Shu-Shen Yeh, Che-Chia Yang, Chin-Hua Wang, Po-Yao Lin, Shin-Puu Jeng, Chia-Hsiang Lin
Filed: 18 Dec 20
APP
Utility
Layout Designs of Integrated Circuits Having Backside Routing Tracks
20 Jan 22
An integrated circuit includes a semiconductor substrate, transistors on the semiconductor, horizontal routing tracks extending in a first direction in a first metal layer, and one or more backside routing tracks extending in the first direction in a backside metal layer.
Wei-An LAI, Shih-Wei PENG, Wei-Cheng LIN, Jiann-Tyng TZENG
Filed: 20 Jul 20
APP
Utility
Three-Dimensional Memory Device and Method
20 Jan 22
A semiconductor device and method of manufacture are provided.
Feng-Cheng Yang, Meng-Han Lin, Han-Jong Chia, Sheng-Chen Wang, Chung-Te Lin
Filed: 11 Sep 20
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