28912 patents
Page 12 of 1446
Utility
Semiconductor Chip
11 Jan 24
A semiconductor chip including a semiconductor substrate, an interconnect structure and a memory cell array is provided.
Bo-Feng Young, Sai-Hooi Yeong, Yu-Ming Lin, Chih-Yu Chang, Han-Jong Chia
Filed: 21 Sep 23
Utility
Gated Tri-state Inverter, and Method of Operating Same
11 Jan 24
A gated tri-state (G3S) inverter includes: first, second and third transistors of a first dopant type (D1 transistors) and first, second and third transistors of a second dopant type (D2 transistors) serially connected between a first reference voltage and second reference voltage, the second dopant type being different than the first dopant type; gate terminals of an alpha one of the noted D1 transistors and an alpha one of the noted D2 transistors being configured to receive an input signal; gate terminals of a beta one of the noted D1 transistors and a beta one of the noted D2 transistors being configured to receive a gating signal; a gate terminal of a gamma one of the noted D2 transistors being configured to receive an enable signal; and a gate terminal of a gamma one of the noted D1 transistors being configured to receive an enable_bar signal.
Tsung-Che LU, Chin-Ming FU, Chih-Hsien CHANG
Filed: 10 Aug 23
Utility
Semiconductor Device and Manufacturing Method Thereof
11 Jan 24
A semiconductor device includes a semiconductor substrate and an interconnection structure.
Chien-Min Lee, Tung-Ying Lee, Cheng-Hsien Wu, Xinyu BAO, Hengyuan Lee, Ying-Yu Chen
Filed: 22 Sep 23
Utility
Three-Dimensional Memory Device and Method
11 Jan 24
In an embodiment, a device includes a first gate structure over a substrate, the first gate structure including a first gate electrode over a first side of a first gate dielectric; a first electrode and a second electrode disposed over a second side of the first gate dielectric opposite the first side; a second gate structure disposed between the first electrode and the second electrode, the second gate structure including a second gate electrode and a second gate dielectric, the second gate dielectric at least laterally surrounding the second gate electrode; and a semiconductor film disposed between the first electrode and the second electrode and at least laterally surrounding the second gate structure, wherein at least one of the first gate dielectric or the second gate dielectric is a memory film.
Meng-Han Lin, Sai-Hooi Yeong, Chia-En Huang, Chi On Chui
Filed: 10 Jan 23
Utility
Magnetic Tunnel Junction Devices
11 Jan 24
A device includes a first dielectric layer, a magnetic tunnel junction (MTJ), an oxide layer, a cap layer, and a second dielectric layer.
Hsi-Wen TIEN, Wei-Hao LIAO, Pin-Ren DAI, Chih-Wei LU, Chung-Ju LEE
Filed: 25 Sep 23
Utility
Ferroelectric Memory Device and Method of Forming the Same
11 Jan 24
A device includes a memory layer over a substrate; a first source/drain structure and a second source/drain structure on the memory layer, wherein the first source/drain structure and the second source drain structure each include a first source/drain layer on the memory layer; a second source/drain layer on the first source/drain layer, wherein the second source/drain layer is different from the first source/drain layer; and a metal layer on the second source/drain layer; and a channel region extending on the memory layer from the first source/drain layer of the first source/drain structure to the first source/drain layer of the second source/drain structure.
Meng-Han Lin, Bo-Feng Young, Sai-Hooi Yeong, Chi On Chui
Filed: 10 Jan 23
Utility
Memory Device and Method of Fabricating the Same
11 Jan 24
A memory device includes a substrate, a reference layer, a tunneling layer, a film stack, and a capping layer.
Po-Sheng Lu, Zhi-Ren Xiao, Nuo Xu, Zhiqiang Wu
Filed: 10 Jul 22
Utility
Memory Cell, Integrated Circuit, and Manufacturing Method of Memory Cell
11 Jan 24
A memory cell includes a bottom electrode, a first dielectric layer, a top electrode, and a variable resistance layer.
Yu-Chao Lin, Tung-Ying Lee, Da-Ching Chiou
Filed: 21 Sep 23
Utility
Memory Cell, Integrated Circuit, and Manufacturing Method of Memory Cell
11 Jan 24
Hengyuan Lee, Yu-Sheng Chen, Cheng-Chun Chang, Xinyu BAO
Filed: 7 Jul 22
Utility
CMP polishing head design for improving removal rate uniformity
9 Jan 24
An apparatus for performing chemical mechanical polish on a wafer includes a polishing head that includes a retaining ring.
Te-Chien Hou, Ching-Hong Jiang, Kuo-Yin Lin, Ming-Shiuan She, Shen-Nan Lee, Teng-Chun Tsai, Yung-Cheng Lu
Filed: 19 Dec 22
Utility
Pellicle and method of using the same
9 Jan 24
A pellicle frame includes a check valve, wherein the check valve is configured to permit gas flow from an interior of the pellicle to an exterior of the pellicle.
Chue San Yoo, Hsin-Chang Lee, Pei-Cheng Hsu, Yun-Yue Lin
Filed: 18 Oct 22
Utility
Polymer layer in semiconductor device and method of manufacture
9 Jan 24
A method of manufacturing a semiconductor device includes applying a polymer mixture over a substrate, exposing and developing at least a portion of the polymer mixture to form a developed dielectric, and curing the developed dielectric to form a dielectric layer.
Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo, Chen-Hua Yu
Filed: 21 Sep 20
Utility
Base layout cell
9 Jan 24
Systems, methods and devices are provided, which can include an engineering change order (ECO) base.
Shang-Hsuan Chiu, Chih-Liang Chen, Hui-Zhong Zhuang, Chi-Yu Lu, Kuang-Ching Chang
Filed: 27 Aug 21
Utility
Inverted integrated circuit and method of forming the same
9 Jan 24
An integrated circuit includes a first and second active region, a first insulating region, and a first and second contact.
Pochun Wang, Yu-Jung Chang, Hui-Zhong Zhuang, Ting-Wei Chiang
Filed: 13 Dec 22
Utility
Embedded ferroelectric memory cell
9 Jan 24
The present disclosure relates to an integrated chip structure.
Tzu-Yu Chen, Kuo-Chi Tu, Wen-Ting Chu, Yong-Shiuan Tsair
Filed: 18 Jul 22
Utility
Compensation word line driver
9 Jan 24
Memory systems are provided.
Chia-Hao Pao, Shih-Hao Lin, Kian-Long Lim
Filed: 20 May 22
Utility
Latch type sense amplifier
9 Jan 24
A device is disclosed and includes an input stage circuit, a switching circuit, and a first latch circuit.
Hua-Hsin Yu, Hung-Jen Liao, Cheng-Hung Lee, Hau-Tai Shieh
Filed: 30 Aug 21
Utility
Back-side deep trench isolation structure for image sensor
9 Jan 24
The present disclosure relates to an image sensor having a photodiode surrounded by a back-side deep trench isolation (BDTI) structure, and an associated method of formation.
Yu-Hung Cheng, Chun-Tsung Kuo, Jiech-Fun Lu, Min-Ying Tsai, Chiao-Chun Hsu, Ching I Li
Filed: 11 Sep 20
Utility
Seed layer for ferroelectric memory device and manufacturing method thereof
9 Jan 24
A method includes: providing a bottom layer; forming a first transistor over a substrate; forming a bottom electrode over the transistor; depositing a first seed layer over the bottom electrode; performing a surface treatment on the first seed layer, wherein after the surface treatment the first seed layer includes at least one of a tetragonal crystal phase and an orthorhombic crystal phase; depositing a dielectric layer over the bottom layer adjacent to the first seed layer, the dielectric layer including an amorphous crystal phase; depositing an upper layer over the dielectric layer; performing a thermal operation on the dielectric layer to thereby convert the dielectric layer into a ferroelectric layer.
Chun-Chieh Lu, Sai-Hooi Yeong, Yu-Ming Lin
Filed: 30 Mar 22
Utility
Method and system of control of epitaxial growth
9 Jan 24
A method of semiconductor fabrication includes positioning a substrate on a susceptor in a chamber and growing an epitaxial feature on the substrate.
Winnie Victoria Wei-Ning Chen, Andrew Joseph Kelly
Filed: 21 Feb 22