16684 patents
Page 2 of 835
Utility
Payload Transportation System
18 Jan 24
System and method for cross-fab wafer transportation are provided.
Chieh Hsu, Guancyun Li, Ching-Jung Chang, Chi-Feng Tung
Filed: 31 Mar 23
Utility
Semiconductor Structure Having Epitaxial Structure
18 Jan 24
A semiconductor structure is provided.
Sai-Hooi YEONG, Yen-Chieh HUANG
Filed: 26 Jul 23
Utility
Finfet with Source/drain Regions Comprising an Insulator Layer
18 Jan 24
An embodiment is a device including a first fin extending from a substrate, a first gate stack over and along sidewalls of the first fin, a first gate spacer disposed along a sidewall of the first gate stack, and a first source/drain region in the first fin and adjacent the first gate spacer.
Tzu-Ching Lin, Tuoh Bin Ng
Filed: 8 Aug 23
Utility
Semiconductor Device
18 Jan 24
A device includes a bottom transistor, a top transistor, and an epitaxial isolation structure.
Chien-Te TU, Hsin-Cheng LIN, Chee-Wee LIU
Filed: 26 Sep 23
Utility
Semiconductor Package and Method
18 Jan 24
A method includes attaching interconnect structures to a carrier substrate, wherein each interconnect structure includes a redistribution structure; a first encapsulant on the redistribution structure; and a via extending through the encapsulant to physically and electrically connect to the redistribution structure; depositing a second encapsulant on the interconnect structures, wherein adjacent interconnect structures are laterally separated by the second encapsulant; after depositing the second encapsulant, attaching a first core substrate to the redistribution structure of at least one interconnect structure, wherein the core substrate is electrically connected to the redistribution structure; and attaching semiconductor devices to the interconnect structures, wherein the semiconductor devices are electrically connected to the vias of the interconnect structures.
Chen-Hua Yu, Wei-Yu Chen, Jiun Yi Wu, Chung-Shi Liu, Chien-Hsun Lee
Filed: 1 Aug 23
Utility
Structure and Formation Method of Semiconductor Device with Dielectric Fin
18 Jan 24
A semiconductor device structure and a formation method are provided.
Hsin-Che CHIANG, Wei-Chih KAO
Filed: 14 Jul 22
Utility
Devices with Reduced Capacitances
18 Jan 24
In one example aspect, the present disclosure is directed to a method.
Yu-Hsin Chan, Cai-Ling Wu, Chang-Wen Chen, Po-Hsiang Huang, Yu-Yu Chen, Kuan-Wei Huang, Jr-Hung Li, Jay Chiu, Ting-Kui Chang
Filed: 8 Aug 23
Utility
Semiconductor Device Structure with Inner Spacer Layer
18 Jan 24
A semiconductor device structure is provided.
Ching-Wei TSAI, Yu-Xuan HUANG, Kuan-Lun CHENG, Chih-Hao WANG, Min CAO, Jung-Hung CHANG, Lo-Heng CHANG, Pei-Hsun WANG, Kuo-Cheng CHIANG
Filed: 28 Sep 23
Utility
Protection Structures for Bonded Wafers
18 Jan 24
A method includes bonding a first wafer to a second wafer.
Ssu-Chiang Weng, Ping-Hao Lin, Fu-Cheng Chang
Filed: 21 Jul 23
Utility
Semiconductor Package and Manufacturing Method Thereof
18 Jan 24
A semiconductor package and a manufacturing method thereof are provided.
Kuei-Sung Chang, Wen-Tuan Lo, Shang-Ying Tsai
Filed: 12 Jul 22
Utility
Contact Plug with Impurity Variation
18 Jan 24
A method includes forming an opening in a dielectric layer, depositing a seed layer in the opening, wherein first portions of the seed layer have a first concentration of impurities, exposing the first portions of the seed layer to a plasma, wherein after exposure to the plasma the first portions have a second concentration of impurities that is less than the first concentration of impurities, and filling the opening with a conductive material to form a conductive feature.
Chung-Chiang Wu, Hsueh Wen Tsau, Chia-Ching Lee, Cheng-Lung Hung, Ching-Hwanq Su
Filed: 26 Jul 23
Utility
Semiconductor Device and Method of Forming the Same
18 Jan 24
A semiconductor device includes a first integrated circuit die and a second integrated circuit die.
Chen-Hsuan Tsai, Tsung-Fu Tsai, Hung-Chih Chen, Chin-Chuan Chang
Filed: 17 Jul 22
Utility
Semiconductor Device Structure and Methods of Forming the Same
18 Jan 24
An interconnection structure, along with methods of forming such, are described.
Hwei-Jay CHU, Chieh-Han WU, Hsin-Chieh YAO, Cheng-Hsiung TSAI, Chung-Ju LEE
Filed: 28 May 23
Utility
Semiconductor Devices and Method for Forming the Same
18 Jan 24
A method includes forming a transistor over a front side of a substrate, in which the transistor comprises a channel region, a gate region over the channel region, and source/drain regions on opposite sides of the gate region; forming a front-side interconnect structure over the transistor, wherein the front-side interconnect structure includes a dielectric layer and conductive features; and bonding the front-side interconnect structure to a carrier substrate via a bonding layer, in which the bonding layer is between the front-side interconnect structure and the carrier substrate, and the bonding layer has a higher thermal conductivity than the dielectric layer of the front-side interconnect structure.
Wen-Sheh HUANG, Yung-Shih CHENG, Jiing-Feng YANG, Yu-Hsiang CHEN, Chii-Ping CHEN
Filed: 26 Sep 23
Utility
Metal Gates of Transistors Having Reduced Resistivity
18 Jan 24
A method includes forming a transistor, which includes forming a gate dielectric on a semiconductor region, forming a gate electrode over the gate dielectric, and forming a source/drain region extending into the semiconductor region.
Chia-Ching Tsai, Yi-Wei Chiu, Li-Te Hsu
Filed: 27 Sep 23
Utility
Semiconductor Structure with Through Via Structure and Method for Manufacturing the Same
18 Jan 24
Semiconductor structures and methods for manufacturing the same are provided.
Yi-Bo LIAO, Li-Zhen YU, Lin-Yu HUANG
Filed: 18 Jul 22
Utility
Transistor Contacts and Methods of Forming the Same
18 Jan 24
In an embodiment, a device includes: a source/drain region over a semiconductor substrate; a dielectric layer over the source/drain region, the dielectric layer including a first dielectric material; an inter-layer dielectric over the dielectric layer, the inter-layer dielectric including a second dielectric material and an impurity, the second dielectric material different from the first dielectric material, a first portion of the inter-layer dielectric having a first concentration of the impurity, a second portion of the inter-layer dielectric having a second concentration of the impurity, the first concentration less than the second concentration; and a source/drain contact extending through the inter-layer dielectric and the dielectric layer to contact the source/drain region, the first portion of the inter-layer dielectric disposed between the source/drain contact and the second portion of the inter-layer dielectric.
Yu-Lien Huang, Tze-Liang Lee, Jr-Hung Li, Chun-Kai Chen
Filed: 6 Jan 23
Utility
Integrated Circuit
18 Jan 24
An integrated circuit includes a first conductive structure including a root portion of the first conductive structure, tine portions that are arranged in a first semiconductor layer, a neck portion surrounded by a film structure.
Shih-Wei PENG, Chia-Tien WU, Jiann-Tyng TZENG
Filed: 26 Sep 23
Utility
Formation of Hybrid Isolation Regions Through Recess and Re-Deposition
18 Jan 24
A method includes forming a semiconductor fin protruding higher than top surfaces of isolation regions.
Chung-Ting Ko, Chi On Chui
Filed: 28 Jul 23
Utility
Semiconductor Device and Manufacturing Method Thereof
18 Jan 24
A semiconductor device includes a semiconductor substrate, at least two source/drain features, at least two source/drain features, one or more channel layers, a gate structure, a first conductive feature, a second conductive feature, and an alignment mark.
Lin-Yu Huang, Chun-Hung Liao
Filed: 13 Jul 22