16684 patents
Page 4 of 835
Utility
Integrated Circuit Including Supervia and Method of Making
18 Jan 24
An integrated circuit includes a substrate; and a first conductive line extending parallel to a top surface of the substrate.
Kam-Tou SIO, Wei-Cheng LIN, Jiann-Tyng TZENG
Filed: 21 Jul 23
Utility
Semiconductor Device with Tunable Threshold Voltage and Method for Manufacturing the Same
18 Jan 24
A semiconductor device includes a channel layer, an interfacial layer, a gate dielectric layer, a gate electrode, dipole elements, and additional elements.
Chansyun David YANG, Huang-Lin CHAO, Hsiang-Pi CHANG, Yen-Tien TUNG, Chung-Liang CHENG, Yu-Chia LIANG, Shen-Yang LEE, Yao-Sheng HUANG, Tzer-Min SHEN, Pinyen LIN
Filed: 15 Jul 22
Utility
Package Structure with Underfill
18 Jan 24
A package structure is provided.
Yu-Sheng LIN, Shin-Puu JENG, Po-Yao LIN, Chin-Hua WANG, Shu-Shen YEH, Che-Chia YANG
Filed: 27 Jul 23
Utility
Semiconductor Device and Method for Manufacturing the Same
18 Jan 24
A method includes forming a gate structure across a channel region from a top view, the gate structure comprising a work function metal and a gate dielectric layer wrapping around the work function metal, the gate dielectric layer having a U-shaped cross-sectional profile; performing a first plasma etching process, by using a chlorine-containing reactant, on the gate structure; performing a second plasma etching process, by using a bromine-containing, reactant on the gate structure.
Jung-Hao CHANG, Li-Te LIN
Filed: 27 Jul 23
Utility
Low-noise Package and Method
18 Jan 24
A package structure includes a first redistribution structure, an insulating material over the first redistribution structure, a die embedded in the insulating material, a second redistribution structure over the die and the insulating material, and a first via extending through the insulating material, wherein the first via includes a first inner conductive core, and a first outer conductive shielding layer, wherein the insulating material is disposed between the first inner conductive core and the first outer conductive shielding layer, and wherein the first outer conductive shielding layer has an annular shape in a top-down view.
Wen-Shiang Liao
Filed: 14 Jul 22
Utility
Semiconductor Structure and Method for Forming the Same
18 Jan 24
A semiconductor structure is provided, and includes a first fin structure, a second fin structure, and a third fin structure over a substrate.
Yun-Ju FAN, Lin-Yu HUANG, Sheng-Tsung WANG, Huan-Chieh SU, Cheng-Chi CHUANG, Chih-Hao WANG
Filed: 14 Jul 22
Utility
Seal Ring for Hybrid-bond
18 Jan 24
A structure includes a first die and a second die.
Chih-Chia Hu, Chun-Chiang Kuo, Sen-Bor Jan, Ming-Fa Chen, Hsien-Wei Chen
Filed: 25 Jul 23
Utility
Device with Self-authentication
18 Jan 24
A device is disclosed.
Haohua ZHOU, Sandeep Kumar GOEL
Filed: 27 Sep 23
Utility
Semiconductor Device and Method of Manufacture
18 Jan 24
A semiconductor device and method of manufacturing that includes a first etch stop layer and a second etch stop layer to prevent delamination and damage to underlying components.
Wei-Chun Liao, Guo-Zhou Huang, Huan-Kuan Su, Yu-Hong Pan, Wen Han Hung, Ling-Sung Wang
Filed: 13 Jul 22
Utility
Semiconductor Memory Devices and Methods of Manufacturing Thereof
18 Jan 24
A semiconductor device includes a first conductive structure extending along a vertical direction and a second conductive structure extending along the vertical direction.
Peng-Chun Liou, Zhiqiang Wu, Ya-Yun Cheng, Yi-Ching Liu, Meng-Han Lin
Filed: 28 Jul 23
Utility
Integrated Circuit Package and Method of Forming Thereof
18 Jan 24
A semiconductor package includes a redistribution structure, a first device and a second device attached to the redistribution structure, the first device including: a first die, a support substrate bonded to a first surface of the first die, and a second die bonded to a second surface of the first die opposite the first surface, where a total height of the first die and the second die is less than a first height of the second device, and where a top surface of the substrate is at least as high as a top surface of the second device, and an encapsulant over the redistribution structure and surrounding the first device and the second device.
Hsien-Wei Chen, Ming-Fa Chen, Ying-Ju Chen
Filed: 21 Jul 23
Utility
Memory Structure and Method of Forming the Same
18 Jan 24
A method of forming a memory structure includes the following steps.
Shih-Hsuan Chien, Meng-Han Lin, Han-Wei Wu, Feng-Cheng Yang
Filed: 2 Aug 23
Utility
Upper Conductive Structure Having Multilayer Stack to Decrease Fabrication Costs and Increase Performance
18 Jan 24
Various embodiments of the present disclosure are directed towards an integrated chip.
Tzu-Yu Lin, Yao-Wen Chang, Chia-Wen Zhong, Yen-Liang Lin
Filed: 9 Aug 23
Utility
Integrated Circuit
18 Jan 24
An integrated circuit includes a metallization pattern having first and second conductive features, an etch stop layer over the metallization pattern, a memory device, a bottom electrode via, a third conductive feature, and a dielectric feature.
Tai-Yen PENG, Chien-Chung HUANG, Yu-Shu CHEN, Sin-Yi YANG, Chen-Jung WANG, Han-Ting LIN, Chih-Yuan TING, Jyu-Horng SHIEH, Hui-Hsien WEI
Filed: 28 Jul 23
Utility
Semiconductor Package and Method of Forming Thereof
18 Jan 24
A semiconductor device includes a redistribution structure, an integrated circuit package attached to a first side of the redistribution structure and a core substrate coupled to a second side of the redistribution structure with a first conductive connector and a second conductive connector.
Jiun Yi Wu, Chen-Hua Yu
Filed: 8 Aug 23
Utility
Sidewall Protection for Pcram Device
18 Jan 24
A phase change random access memory (PCRAM) device includes a memory cell overlying an inter-metal dielectric (IMD) layer, a protection coating, and a first sidewall spacer.
Yu-Chao LIN, Yuan-Tien TU, Shao-Ming YU, Tung-Ying LEE
Filed: 27 Sep 23
Utility
Die Attached Leveling Control by Metal Stopper Bumps
18 Jan 24
In some embodiments, the present disclosure relates to an integrated chip (IC), including a substrate, a first die disposed over the substrate, a metal wire attached to a frontside of the first die, and a first plurality of die stopper bumps disposed along a backside of the first die and configured to control an angle of operation of the first die.
Wei-Jhih Mao, Kuei-Sung Chang, Shang-Ying Tsai
Filed: 7 Aug 23
Utility
Method for Forming a Memory Device at a Backside of a Wafer Substrate, and Memory Cell Including a Memory Device at a Backside of a Wafer Substrate
18 Jan 24
A method is provided for forming a memory device on a backside portion of a wafer substrate.
Chung-Liang CHENG, Lin-Yu HUANG, Wen-Ting LAN, Li-Zhen YU, Huang-Lin CHAO, Pinyen LIN
Filed: 15 Jul 22
Utility
Through-dielectric Vias for Direct Connection and Method Forming Same
18 Jan 24
A method includes bonding a tier-1 device die to a carrier, forming a first gap-filling region to encapsulate the tier-1 device die, forming a first redistribution structure over and electrically connected to the tier-1 device die, and bonding a tier-2 device die to the tier-1 device die.
Ming-Fa Chen, Chuan-An Cheng, Sung-Feng Yeh, Chih-Chia Hu
Filed: 6 Aug 23
Utility
Lamination Process, and Manufacturing Method of Semiconductor Package Using a Chuck
18 Jan 24
A lamination chuck for lamination of film materials includes a support layer and a top layer.
Wei-Jie Huang, Yu-Ching Lo, Ching-Pin Yuan, Wen-Chih Lin, Cheng-Yu Kuo, Yi-Yang Lei, Ching-Hua Hsieh
Filed: 2 Aug 23