16684 patents
Page 5 of 835
Utility
Package and Method of Fabricating the Same
18 Jan 24
Packages and methods of fabricating the same are provided.
Hsien-Wei Chen, Ming-Fa Chen
Filed: 31 Jul 23
Utility
Molded Dies in Semiconductor Packages and Methods of Forming Same
18 Jan 24
A package includes an interposer having a first redistribution structure; a first die directly bonded to a first surface of the first redistribution structure with a dielectric-to-dielectric bond and a metal-to-metal bond; a second die directly bonded to the first surface of the first redistribution structure with a dielectric-to-dielectric bond and a metal-to-metal bond; an encapsulant around the first die and the second die; and a plurality of conductive connectors on a second side of the first redistribution structure opposite to the first die and the second die.
Jie Chen, Hsien-Wei Chen, Ming-Fa Chen
Filed: 7 Aug 23
Utility
Method of Making Amphi-fet Structure and Method of Designing
18 Jan 24
A method of making a semiconductor device includes forming a first active region on a first side of a substrate.
Chih-Yu LAI, Chih-Liang CHEN, Chi-Yu LU, Shang-Syuan CIOU, Hui-Zhong ZHUANG, Ching-Wei TSAI, Shang-Wen CHANG
Filed: 27 Jul 23
Utility
Semiconductor Devices and Methods of Manufacture
18 Jan 24
Transistors of different types of electronic devices on the same semiconductor substrate are configured with different transistor attributes to increase the performance of the different types of electronic devices.
Ta-Chun LIN, Kuo-Hua PAN, Jhon Jhy LIAW
Filed: 21 Jul 23
Utility
Bent Fin Devices
18 Jan 24
Semiconductor devices and methods of forming the same are provided.
Jiun-Ming Kuo, Pei-Ling Gao, Chen-Hsuan Liao, Hung-Ju Chou, Chih-Chung Chang, Che-Yuan Hsu
Filed: 28 Jul 23
Utility
Method to Embed Planar Fets with Finfets
18 Jan 24
Various embodiments of the present disclosure are directed towards a method to embed planar field-effect transistor (FETs) with fin field-effect transistors (finFETs).
Harry-Hak-Lay Chuang, Wei Cheng Wu, Li-Feng Teng, Li-Jung Liu
Filed: 4 Aug 23
Utility
Semiconductor Devices with Backside Contacts and Isolation
18 Jan 24
A semiconductor structure includes an isolation structure, a source/drain region over the isolation structure, a gate structure over the isolation structure and adjacent to the source/drain region, an interconnect layer over the source/drain region and the gate structure, an isolating layer below the gate structure, and a contact structure under the source/drain region.
Chun-Yuan Chen, Huan-Chieh Su, Cheng-Chi Chuang, Chih-Hao Wang
Filed: 21 Jul 23
Utility
Semiconductor Device and Method
18 Jan 24
In an embodiment, a device includes: a first fin extending from a substrate; a second fin extending from the substrate; a gate spacer over the first fin and the second fin; a gate dielectric having a first portion, a second portion, and a third portion, the first portion extending along a first sidewall of the first fin, the second portion extending along a second sidewall of the second fin, the third portion extending along a third sidewall of the gate spacer, the third portion and the first portion forming a first acute angle, the third portion and the second portion forming a second acute angle; and a gate electrode on the gate dielectric.
Shahaji B. More, Chandrashekhar Prakash Savant
Filed: 31 Jul 23
Utility
Semiconductor Device and Method
18 Jan 24
A method includes forming first devices in a first region of a substrate, wherein each first device has a first number of fins; forming second devices in a second region of the substrate that is different from the first region, wherein each second device has a second number of fins that is different from the first number of fins; forming first recesses in the fins of the first devices, wherein the first recesses have a first depth; after forming the first recesses, forming second recesses in the fins of the second devices, wherein the second recesses have a second depth different from the first depth; growing a first epitaxial source/drain region in the first recesses; and growing a second epitaxial source/drain region in the second recess.
Chih-Yun Chin, Yen-Ru Lee, Chien-Chang Su, Yan-Ting Lin, Chien-Wei Lee, Bang-Ting Yan, Heng-Wen Ting, Chii-Horng Li, Yee-Chia Yeo
Filed: 1 Aug 23
Utility
Finfet Device and Method
18 Jan 24
A device includes a fin extending from a semiconductor substrate; a gate stack over the fin; a spacer on a sidewall of the gate stack; a source/drain region in the fin adjacent the spacer; an inter-layer dielectric layer (ILD) extending over the gate stack, the spacer, and the source/drain region; a contact plug extending through the ILD and contacting the source/drain region; a dielectric layer including a first portion on a top surface of the ILD and a second portion extending between the ILD and the contact plug, wherein a top surface of the second portion is closer to the substrate than the top surface of the ILD; and an air gap between the spacer and the contact plug, wherein the second portion of the dielectric layer seals the top of the air gap.
Tsai-Jung Ho, Tze-Liang Lee
Filed: 1 Aug 23
Utility
Semiconductor Device and Method
18 Jan 24
A method includes etching a substrate to form a semiconductor fin, forming a gate stack on a top surface and sidewalls of the semiconductor fin, and forming a first recess in the semiconductor fin on a side of the gate stack, wherein forming the first recess comprises, performing a first etching process to form a first portion of the first recess, depositing a first dielectric layer on sidewalls of the gate stack and the first portion of the first recess, performing a second etching process to form a second portion of the first recess using the first dielectric layer as a mask, wherein the second portion of the first recess extends under the gate stack, and performing a third etching process to remove the first dielectric layer.
Yu-Rung Hsu
Filed: 4 Aug 23
Utility
Grid Structure with at Least Partially Angled Sidewalls
18 Jan 24
A grid structure in a pixel array may be at least partially angled or tapered toward a top surface of the grid structure such that the width of the grid structure approaches a near-zero width near the top surface of the grid structure.
Wei-Lin CHEN, Ching-Chung SU, Chun-Hao CHOU, Kuo-Cheng LEE
Filed: 2 Aug 23
Utility
Optical Structure and Method for Manufacturing the Same
18 Jan 24
An optical structure and methods of forming an optical structure are provided.
Chieh-En CHEN, Chen-Hsien LIN, Tzu-Hsuan HSU, Cheng Yu HUANG, Wei-Chieh CHIANG
Filed: 15 Jul 22
Utility
Dielectric Structure for Small Pixel Designs
18 Jan 24
Various embodiments of the present disclosure are directed towards an image sensor.
Wei Long Chen, Wen-I Hsu, Feng-Chi Hung, Jen-Cheng Liu, Dun-Nian Yaung
Filed: 4 Jan 23
Utility
Enhanced Trench Isolation Structure
18 Jan 24
The present disclosure relates to an image sensor comprising a substrate.
Min-Ying Tsai, Cheng-Te Lee, Rei-Lin Chu, Ching I Li, Chung-Yi Yu
Filed: 20 Jul 23
Utility
Composite Bsi Structure and Method of Manufacturing the Same
18 Jan 24
Various embodiments of the present application are directed towards image sensors including composite backside illuminated (CBSI) structures to enhance performance.
Wei Chuang Wu, Dun-Nian Yaung, Feng-Chi Hung, Jen-Cheng Liu, Jhy-Jyi Sze, Keng-Yu Chou, Yen-Ting Chiang, Ming-Hsien Yang, Chun-Yuan Chen
Filed: 21 Jul 23
Utility
Trench Isolation Structure for Image Sensors
18 Jan 24
Various embodiments of the present disclosure are directed towards an image sensor, and a method for forming the image sensor, in which an inter-pixel trench isolation structure is defined by a low-transmission layer.
Cheng Yu Huang, Chun-Hao Chuang, Keng-Yu Chou, Wei-Chieh Chiang, Chin-Chia Kuo, Wen-Hau Wu, Hua-Mao Chen, Chih-Kung Chang
Filed: 8 Aug 23
Utility
Stacked Substrate Structure with Inter-tier Interconnection
18 Jan 24
The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure.
Jeng-Shyan Lin, Dun-Nian Yaung, Jen-Cheng Liu, Hsun-Ying Huang, Wei-Chih Weng, Yu-Yang Shen
Filed: 21 Jul 23
Utility
Method of Forming Self Aligned Grids In Bsi Image Sensor
18 Jan 24
A method of fabricating self-aligned grids in a BSI image sensor is provided.
Tsun-Kai Tsao, Jiech-Fun Lu, Shih-Pei Chou, Wei Chuang Wu
Filed: 28 Sep 23
Utility
Semiconductor Device and Method for Forming the Same
18 Jan 24
A method includes forming a first capacitor electrode; forming a first oxygen-blocking layer on the first capacitor electrode; forming an capacitor insulator layer on the first oxygen-blocking layer; forming a second oxygen-blocking layer on the capacitor insulator layer; forming a second capacitor electrode on the second oxygen-blocking layer; and forming a first contact plug that is electrically coupled to the first capacitor electrode and a second contact plug that is electrically coupled to the second capacitor electrode.
Cheng-Hao Hou, Shin-Hung Tsai, Da-Yuan Lee, Chi On Chui
Filed: 10 Jan 23