5344 patents
Utility
Management of Host File-system Defragmentation In a Data Storage Device
18 Jan 24
A data storage device having a flash translation layer configured to handle file-system defragmentation in a manner that avoids, reduces, and/or optimizes physical data movement in flash memory.
Judah Gamliel Hahn, Ramanathan Muthiah, Bala Siva Kumar Narala, Narendhiran Chinnaanangur Ravimohan
Filed: 15 Jul 22
Utility
Multi-stage Data Compaction In Nand
18 Jan 24
Technology is disclosed herein for multi-stage data compaction.
Harish Gajula, Bhanushankar Doni
Filed: 14 Jul 22
Utility
Logical-to-physical Mapping for Defragmentation of Host File System In a Data Storage Device
18 Jan 24
A data storage device having a flash translation layer configured to handle file-system defragmentation in a manner that substantially avoids physical data movement in a flash memory.
Judah Gamliel Hahn, Ramanathan Muthiah, Bala Siva Kumar Narala, Narendhiran Chinnaanangur Ravimohan
Filed: 15 Jul 22
Utility
Load/unload Ramp for High-capacity Hard Disk Drive
18 Jan 24
A multi-slope load/unload ramp for a hard disk drive includes an inner first portion having a non-horizontal first slope and an adjacent outer second portion having a different non-horizontal second slope.
Taichi Nakamura, Biao Sun, Katsuhide Tanaka
Filed: 13 Jul 22
Utility
Alternating-bias signal resistance detection for resistive temperature detectors in disk drives
16 Jan 24
Various illustrative aspects are directed to a data storage device comprising a slider with a resistive temperature detector (RTD) having a first resistance electrically connected to a first amplifier and a plurality of controlled current sources and switches, and one or more processing devices configured to: control the switches to generate an alternating-bias signal having a first clock frequency for biasing the first resistance, modulate an input signal of the first amplifier using the first clock frequency to generate a modulated signal, demodulate an amplified modulated signal at an output of a second amplifier using the first clock frequency to generate a resistance detection signal, the second amplifier coupled to the first amplifier, and process the resistance detection signal to determine the first resistance and/or a change in value of the first resistance.
John Contreras, Joey M. Poss, Ronald Chang, Bernhard E. Knigge
Filed: 9 Aug 22
Utility
Indexless logical-to-physical translation table
16 Jan 24
An indexless logical-to-physical translation table (L2PTT).
Oleg Kragel, Vijay Sivasankaran
Filed: 12 May 22
Utility
Multiple indirection sizes for logical-to-physical translation tables
16 Jan 24
Multiple logical-to-physical translation tables (L2PTTs) for data storage devices having indirection units of different sizes.
Arvind Kumar V M, Ravishankar Surianarayanan
Filed: 16 May 22
Utility
Block allocation for multi-CE/die structure SSD
16 Jan 24
The present disclosure generally relates to methods and systems for allocating free blocks as decommissioned blocks to replace bad blocks.
Min Young Kim, Min Woo Lee, Dhayanithi Rajendiran, Hiep Tran
Filed: 20 Apr 21
Utility
Loop dependent word line ramp start time for program verify of multi-level NAND memory
16 Jan 24
To reduce spikes in the current used by a NAND memory die during a write operation using smart verify, different amounts of delay are introduced into the loops of the programing algorithm.
Abu Naser Zainuddin, Jiahui Yuan, Toru Miwa
Filed: 13 Sep 22
Utility
Proactive hardening of data storage system
16 Jan 24
Disclosed are systems and methods for proactively recovering files stored in flash storage devices.
Chakradhar Kommuri
Filed: 23 Jun 22
Utility
Smart video surveillance system using a neural network engine
16 Jan 24
A surveillance system includes at least one image or video capture device and a controller configured to determine a change in location for the at least one image or video capture device from a first location to a second location.
Shaomin Xiong, Toshiki Hirano, Haoyu Wu
Filed: 24 Dec 21
Utility
SOT reader using BiSb topological insulator
16 Jan 24
The present disclosure generally relate to spin-orbit torque (SOT) devices.
Quang Le, Brian R. York, Xiaoyong Liu, Son T. Le, Cherngye Hwang, Michael A. Gribelyuk, Xiaoyu Xu, Kuok San Ho, Hisashi Takano, Julian Sasaki, Huy H. Ho, Khang H. D. Nguyen, Nam Hai Pham
Filed: 25 Mar 22
Utility
Systems and methods for staggering read operation of sub-blocks
16 Jan 24
A memory device with one or more planes having sub-blocks is disclosed.
Yu-Chung Lien, Deepanshu Dutta, Tai-Yuan Tseng
Filed: 9 Nov 21
Utility
Field effect transistors with reduced gate fringe area and method of making the same
16 Jan 24
A semiconductor structure includes at least two field effect transistors.
Takahito Fujita, Hiroyuki Ogawa, Kiyokazu Shishido
Filed: 7 Oct 21
Utility
Three-dimensional memory device with electrically conductive layers containing vertical tubular liners and methods for forming the same
16 Jan 24
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, and memory opening fill structures located within the memory openings.
Rahul Sharangpani, Raghuveer S. Makala, Fei Zhou, Adarsh Rajashekhar
Filed: 11 Jun 21
Utility
Three-dimensional memory device including laterally-undulating memory material layers and methods for forming the same
16 Jan 24
A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel and a memory material layer.
Tatsuya Hinoue, Zhixin Cui
Filed: 4 Mar 21
Utility
Three-dimensional Memory Device Containing Etch Stop Metal Plates for Backside Via Structures and Methods for Forming the Same
11 Jan 24
A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers that is located on a front side of at least one semiconductor material layer; memory openings vertically extending through the alternating stack; memory opening fill structures; a dielectric material portion contacting sidewalls of the insulating layers of the alternating stack.
Yusuke Yoshida, Teruo Okina, Kenichi Okabe
Filed: 5 Jul 22
Utility
Three-dimensional Memory Device Containing Etch Stop Metal Plates for Backside Via Structures and Methods for Forming the Same
11 Jan 24
A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers that is located on a front side of at least one semiconductor material layer; memory openings vertically extending through the alternating stack; memory opening fill structures; a dielectric material portion contacting sidewalls of the insulating layers of the alternating stack.
Hiroaki Namba
Filed: 5 Jul 22
Utility
Three-dimensional Memory Device Including Variable Thickness Semiconductor Channels and Method of Forming the Same
11 Jan 24
A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, where the electrically conductive layers include word line electrically conductive layers and a first select-level electrically conductive layer, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a memory film and a vertical semiconductor channel.
Tadashi NAKAMURA, Nobuyuki FUJIMURA
Filed: 7 Jul 22
Utility
Magnetoresistive Memory Device Including a Magnetoresistance Amplification Layer
11 Jan 24
A magnetoresistive memory cell includes a first electrode, a second electrode that is spaced from the first electrode, a magnetic tunnel junction layer stack located between the first electrode and the second electrode, the magnetic tunnel junction layer stack containing, from one side to another, a reference layer having a fixed reference magnetization direction, a tunnel barrier layer comprising a dielectric material, and a free layer, and an asymmetric magnetoresistance layer located between the magnetic tunnel junction layer stack and one of the first electrode and the second electrode.
Goran MIHAJLOVIC, Lei WAN
Filed: 5 Jul 22