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Western Digital (WDC)

Utility
Thermal sensor array for molecule detection and related detection schemes
10 May 22
Disclosed herein are detection devices, systems including such detection devices, and methods of using such detection devices.
Patrick Braganca, Daniel Bedau
Filed: 26 Nov 19
Utility
Storage system and method for host memory access
10 May 22
A storage system and method for host memory access are provided.
Rotem Sela, Amir Shaharabany, Eliad Adi Klein
Filed: 14 May 20
Utility
Decentralized data processing architecture
10 May 22
A system and method for decentralized data processing includes receiving, by a first data processing unit of a data processing unit array, a user request and sending, by the first data processing unit, the user request to at least one of other data processing units of the data processing unit array.
Viacheslav Dubeyko, Luis Vitório Cargnini
Filed: 13 Nov 18
Utility
Method and system for identifying erased memory areas
10 May 22
The subject technology provides for scanning blocks of a flash memory device for erased pages.
Richard David Barndt, Seyhan Karakulak, Scott Kayser, Majid Nemati Anaraki, Anthony Dwayne Weathers
Filed: 18 Dec 20
Utility
Realization of binary neural networks in NAND memory arrays
10 May 22
Use of a NAND array architecture to realize a binary neural network (BNN) allows for matrix multiplication and accumulation to be performed within the memory array.
Won Ho Choi, Pi-Feng Chiu, Wen Ma, Minghai Qin, Gerrit Jan Hemink, Martin Lueker-Boden
Filed: 28 Mar 19
Utility
Storage system and method for improved playback analysis
10 May 22
A storage system and method for improved playback analysis are provided.
Ramanathan Muthiah, Judah Gamliel Hahn
Filed: 13 Mar 20
Utility
Heat-assisted magnetic recording (HAMR) head with heat sink material adjacent the waveguide
10 May 22
A heat-assisted magnetic recording (HAMR) head has a gas-bearing slider that supports a near-field transducer (NFT) and a main magnetic pole.
Takuya Matsumoto
Filed: 10 Feb 21
Utility
Pre-charge timing control for peak current based on data latch count
10 May 22
Aspects of a storage device including a memory and a controller are provided which allow for reduction of current during program operations using pre-charge timing control based on an inhibit bit line count acquired from data latches.
Yu-Chung Lien, Juan Lee, Huai-Yuan Tseng
Filed: 29 May 20
Utility
Signal preserve in MRAM during reading
10 May 22
Apparatuses and techniques are described for reading MRAM memory cells.
Ward Parkinson, James O'Toole, Nathan Franklin, Thomas Trent
Filed: 2 Oct 20
Utility
Reduced verify scheme during programming based on spacing between verify levels
10 May 22
Apparatuses and techniques are described for optimizing a program operation in a memory device in which groups of memory cells are programmed from checkpoint states to respective data states.
Huiwen Xu, Jun Wan, Bo Lei
Filed: 9 Dec 20
Utility
Transferring computational operations to controllers of data storage devices
3 May 22
Systems and methods for offloading computational operations.
Eswaran Subramaniam, Sathyanarayanan Subramanian, Jatin Gaur
Filed: 31 Oct 18
Utility
Adaptive folding for integrated memory assembly
3 May 22
A non-volatile storage system includes a memory controller connected to an integrated memory assembly.
Eran Sharon, Alex Bazarsky, Idan Alrod
Filed: 9 May 20
Utility
Persistent version control for data transfer between heterogeneous data stores
3 May 22
Example distributed storage systems, version control managers, and methods provide persistent version control for data transfers between heterogeneous data stores.
Tomy Ammuthan Cheru, Muhammad Tanweer Alam, Vibhor Arunkumar Patale
Filed: 22 Mar 19
Utility
Enhanced multistate verify techniques in a memory device
3 May 22
A method comprises determining a verify voltage for a next iteration of a verify operation to be performed on memory cells a first set of memory cells of a selected word line, and determining data states for a second set of memory cells of at least one neighboring word line.
Muhammad Masuduzzaman, Deepanshu Dutta
Filed: 12 Jun 20
Utility
Three-dimensional memory device with dielectric wall support structures and method of forming the same
3 May 22
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located between line trenches, a first memory array region and a second memory array region, and a pair of dielectric wall structures located between the first line trench and the second line trench and between the memory array regions.
Tomohiro Kubo
Filed: 30 Sep 20
Utility
Semiconductor die containing dummy metallic pads and methods of forming the same
3 May 22
A first semiconductor die includes first semiconductor devices located over a first substrate, first interconnect-level dielectric layers embedding first metal interconnect structures and located over the first semiconductor devices, a first pad-level dielectric layer embedding first bonding pads and located over the first interconnect-level dielectric layers, and first edge seal structures laterally surrounding the first semiconductor devices.
Teruo Okina
Filed: 20 May 20
Utility
Three-dimensional memory device containing a shared word line driver across different tiers and methods for making the same
3 May 22
A semiconductor structure includes a peripheral circuit, a first three-dimensional memory array overlying the peripheral circuit and including a first alternating stack of first insulating layers and first electrically conductive layers containing first word lines and first select lines, and first memory stack structures vertically extending through the first alternating stack, and a second three-dimensional memory array overlying the first three-dimensional memory array and including a second alternating stack of second insulating layers and second electrically conductive layers containing second word lines and second select lines, and second memory stack structures vertically extending through the second alternating stack.
Hiroyuki Ogawa, Ken Oowada, Mitsuteru Mushiga
Filed: 5 Nov 20
Utility
Three-dimensional memory device including a silicon-germanium source contact layer and method of making the same
3 May 22
A memory device includes a silicon-germanium source contact layer, an alternating stack of insulating layers and electrically conductive layers located over the silicon-germanium source contact layer, and a memory stack structure vertically extending through the alternating stack.
Ashish Baraskar, Raghuveer S. Makala, Peter Rabkin
Filed: 24 Aug 20
Utility
Gate material-based capacitor and resistor structures and methods of forming the same
3 May 22
At least one of a capacitor or a resistor structure can be formed concurrently with formation of a field effect transistor by patterning a gate dielectric layer into gate dielectric and into a first node dielectric or a first resistor isolation dielectric, and by patterning a semiconductor layer into a gate electrode and into a second electrode of a capacitor or a resistor strip.
Hokuto Kodate, Hiroyuki Ogawa, Dai Iwata, Mitsuhiro Togo
Filed: 28 Aug 20
Utility
Extensible storage system and method
26 Apr 22
A storage system controller chip includes routing circuitry comprising a host interface for coupling to a host device and an extension interface for coupling to a secondary controller chip.
Rajesh Koul, Rodney N. Mullendore, James J. Walsh
Filed: 23 Mar 21
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