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GSI Technology (GSIT)

Utility
Write data processing methods associated with computational memory cells
22 Feb 22
A write data processing method associated with computational memory cells formed as a memory/processing array provides the ability to shift data between adjacent bit lines in each section of the memory/processing array or the same relative bit lines in adjacent sections of the memory/processing array.
Bob Haig, Eli Ehrman, Chao-Hung Chang, Mu-Hsiang Huang
Filed: 9 Oct 20
Utility
Storage array circuits and methods for computational memory cells
18 Jan 22
A storage array for computational memory cells formed as a memory/processing array provides storage of the data without using the more complicated computational memory cells for storage.
Lee-Lean Shu, Park Soon-Kyu, Paul M. Chiang
Filed: 4 Jun 18
Utility
Read data processing circuits and methods associated with computational memory cells
21 Dec 21
A read register is provided that captures and stores the read result on a read bit line connected to a set of computational memory cells.
Bob Haig, Eli Ehrman, Chao-Hung Chang, Mu-Hsiang Huang
Filed: 28 May 20
Utility
Results processing circuits and methods associated with computational memory cells
7 Dec 21
A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array (having a plurality of bit line sections) provides a mechanism to logically combine the computation results across multiple bit line sections in a section and across multiple sections, and transmit the combined result as an output of the processing array and/or store the combined result into one or more of those multiple bit line sections.
Bob Haig, Eli Ehrman, Dan Ilan, Patrick Chuang, Chao-Hung Chang, Mu-Hsiang Huang
Filed: 13 Dec 19
Utility
Processing array device that performs one cycle full adder operation and bit line read/write logic features
7 Dec 21
Lee-Lean Shu, Bob Haig, Chao-Hung Chang
Filed: 6 Oct 20
Utility
Secure Similarity Search for Sensitive Data
18 Nov 21
A system including a secure, in-memory unit implemented on an associative processing unit (APU), for creating encrypted vectors.
Mark WRIGHT, Avidan AKERIB
Filed: 9 May 21
Utility
Memory Device for Determining an Extreme Value
11 Nov 21
A method to determine an extreme value of a plurality of data candidates includes storing each data candidate of a plurality of data candidates in a separate column of an associative memory, initializing a row of marker bits by setting each marker bit to a value of 1, computing a subsequent row of marker bits by performing in parallel a Boolean AND operation between a previous row of marker bits and a row of bits of the data candidates, starting with the row of most significant bits of the data candidates, performing a Boolean OR operation between the marker bits in the subsequent row of marker bits to generate a subsequent RSP value, identifying the extreme value from among the plurality of data candidates when there is only one marker bit having a value of 1 in the subsequent row of marker bits coinciding with when said subsequent RSP value is a 1, and if the identifying is false, repeating the computing on a row of next most significant bits, performing and identifying until the identifying is true.
Avidan AKERIB, Eli EHRMAN
Filed: 26 Jul 21
Utility
Satellite Imagery
28 Oct 21
A system for detecting changes between two temporally different images includes an image divider, a Convolutional Neural Network (CNN) feature encoder, an image alignment system, a feature comparator, a CNN feature decoder and segmenter, and a block combiner.
Elona EREZ, Avidan AKERIB
Filed: 12 Apr 21
Utility
Computational memory cell and processing array device using memory cells
19 Oct 21
A memory cell that may be used for computation and processing array using the memory cell are capable to performing a logic operation including a boolean AND, a boolean OR, a boolean NAND or a boolean NOR.
Lee-Lean Shu, Chao-Hung Chang, Avidan Akerib
Filed: 8 Jun 20
Utility
Efficient Similarity Search
23 Sep 21
A system for measuring similarity between a binary query vector and a plurality of binary candidate vectors includes a storage unit and a processor.
Samuel LIFSCHES
Filed: 8 Jul 20
Utility
Molecular Similarity Search
16 Sep 21
A system for finding similar molecules to a query molecule includes a GCN, a PFS vector extractor, a compensated vector comparator (CVC) and a candidate vector selector.
Elona EREZ
Filed: 14 Mar 21
Utility
Iterative Binary Division with Carry Prediction
26 Aug 21
A method for binary division includes the steps of having a current remainder provided as a sum bit-vector and a carry bit-vector, performing a carry save add operation between the sum bit-vector and the carry bit-vector and a two's complement representation of a denominator to produce a temporary sum and a temporary carry, predicting a sign bit of a full total of the temporary sum and the temporary carry and updating the remainder with the temporary sum and the temporary carry and incrementing a quotient if the sign bit is 0.
Dan ILAN
Filed: 19 Jan 21
Utility
Write data processing circuits and methods associated with computational memory cells
17 Aug 21
A write data processing apparatus and method associated with computational memory cells formed as a memory/processing array provides the ability to shift data between adjacent bit lines in each section of the memory/processing array or the same relative bit lines in adjacent sections of the memory/processing array.
Bob Haig, Eli Ehrman, Chao-Hung Chang, Mu-Hsiang Huang
Filed: 26 Dec 19
Utility
Responder signal circuitry for memory arrays finding at least one cell with a predefined value
27 Jul 21
A memory device includes a memory array of non-volatile memory cells arranged in rows and columns and responder signal circuitry.
Avidan Akerib, Eli Ehrman
Filed: 13 Dec 17
Utility
Computational Memory Cell and Processing Array Device Using the Memory Cells for Xor and Xnor Computations
22 Jul 21
A memory cell and processing array that has a plurality of memory are capable of performing logic functions, including an exclusive OR (XOR) or an exclusive NOR (XNOR) logic function.
Lee-Lean Shu, Eli Ehrman
Filed: 2 Apr 21
Utility
Computational Memory Cell and Processing Array Device Using the Memory Cells for Xor and Xnor Computations
22 Jul 21
A memory cell and processing array that has a plurality of memory are capable of performing logic functions, including an exclusive OR (XOR) or an exclusive NOR (XNOR) logic function.
Lee-Lean Shu, Eli Ehrman
Filed: 2 Apr 21
Utility
Results Processing Circuits and Methods Associated with Computational Memory Cells
15 Jul 21
A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array (having a plurality of bit line sections) provides a mechanism to logically combine the computation results across multiple bit line sections in a section and across multiple sections, and transmit the combined result as an output of the processing array and/or store the combined result into one or more of those multiple bit line sections.
Bob HAIG, Eli EHRMAN, Dan ILAN, Patrick CHUANG, Chao-Hung CHANG, Mu-Hsiang HUANG
Filed: 27 Oct 20
Utility
Memory Matrix Multiplication and Its Usage In Neural Networks
8 Jul 21
A method for in memory computation of a neural network, the neural network having weights arranged in a matrix, includes previously storing the matrix in an associated memory device, receiving an input arranged in a vector and storing it in the memory device, and in-memory, computing an output of the network using the input and the weights.
Avidan AKERIB, Pat LASSERRE
Filed: 7 Mar 21
Utility
One by One Selection of Items of a Set
17 Jun 21
An associative memory array includes a plurality of associative memory cells arranged in rows and columns where each first cell in a first row and in a first column has access to a content of a second cell in a second row in an adjacent column.
Moshe LAZER, Eli EHRMAN
Filed: 2 Mar 21
Utility
Orthogonal Data Transposition System and Method During Data Transfers To/from a Processing Array
10 Jun 21
A device and method for facilitating orthogonal data transposition during data transfers to/from a processing array and a storage memory since the data words processed by the processing array (using computational memory cells) are stored orthogonally to how the data words are stored in storage memory.
Bob HAIG, Patrick CHUANG, Chih TSENG, Mu-Hsiang HUANG
Filed: 28 Oct 20
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