29 patents
Utility
Integrated module assembly for optical integrated circuits
2 Jan 24
An integrated module assembly can include: an optical integrated circuit having first and second optical devices; a PCB having first and second holes therein, where the optical integrated circuit is coupled upside down to a first side of the PCB; and first and second lenses coupled to a second side of the PCB, where the first and second sides of the PCB are opposite thereto; and where the first lens is in alignment with the first hole and the first optical device, and the second lens is in alignment with the second hole and the second optical device.
Bard M. Pedersen
Filed: 2 Dec 20
Utility
Nonvolatile memory devices, systems and methods with switching charge pump architectures
18 Jul 23
A memory device can include a nonvolatile memory (NVM) cell array, data path circuits, coupled between the NVM cell array and an output of the device, that are configured to enable access to the NVM cell array via a plurality of bit lines.
Stephen Trinh, Duong Vinh Hao, Nguyen Khac Hieu, Hendrik Hartono, John Dinh, Shane Charles Hollmer
Filed: 2 Jul 21
Utility
Pseudo physically unclonable functions (PUFS) using one or more addressable arrays of elements having random/pseudo-random values
27 Dec 22
An integrated circuit device can include a plurality of nonvolatile memory elements having values that vary randomly or pseudo-randomly from one another; a selection circuit configured to select a plurality of nonvolatile memory elements that vary randomly or pseudo-randomly in response to a received challenge value; and sense circuits configured to generate a response value based on the values of the selected nonvolatile memory elements.
John R. Jameson, David Kim, Foroozan Sarah Koushan
Filed: 13 Sep 19
Utility
Memory Devices and Methods Having Multiple Acknowledgements In Response to a Same Instruction
3 Nov 22
A memory device A memory device can include a serial interface (IF) configured to receive an operational code (op code) of no less than 16-bits and provide a plurality of acknowledgement values in response to the received op code.
Paul Hill
Filed: 18 Jul 22
Utility
Memory devices and methods having instruction acknowledgement
19 Jul 22
A system can include memory circuits configured to execute memory access operations in response to commands, a serial interface circuit configured to receive commands, including at least a first type command, and a controller circuit configured to generate a command complete acknowledgement that is output at the interface circuit after an operation indicated by the first type command has been completed by the memory circuits.
Paul Hill
Filed: 14 Nov 16
Utility
Memory latency reduction in XIP mode
21 Jun 22
A method of controlling a read request can include: receiving, in a host device, the read request from a bus master, where the host device is coupled to a memory device by an interface; determining a configuration state of the read request; comparing an attribute of the read request against a predetermined attribute stored in the host device; adjusting the configuration state of the read request when the attribute of the read request matches the predetermined attribute; and sending the read request with the adjusted configuration state from the host device to the memory device via the interface.
Gideon Intrater, Bard Pedersen
Filed: 24 Sep 20
Utility
Memory Latency Reduction In Xip Mode
24 Mar 22
A method of controlling a read request can include: receiving, in a host device, the read request from a bus master, where the host device is coupled to a memory device by an interface; determining a configuration state of the read request; comparing an attribute of the read request against a predetermined attribute stored in the host device; adjusting the configuration state of the read request when the attribute of the read request matches the predetermined attribute; and sending the read request with the adjusted configuration state from the host device to the memory device via the interface.
Gideon Intrater, Bard Pedersen
Filed: 24 Sep 20
Utility
Pulse Width Signal Overlap Compensation Techniques
9 Dec 21
A pulse signal compensation circuit of a pulse generator can include a pulse measurement circuit and a compensation generator circuit.
Shiyu Zhou, Cormac O'Sullivan
Filed: 20 Aug 21
Utility
Wideband Receivers and Methods of Operation
9 Dec 21
A receiver can include a first set of one or more amplifier stages configured to amplify input signals in a plurality of communication bands.
Rishi Singh, Darren Collins, Cormac O'Sullivan
Filed: 20 Aug 21
Utility
Time Interleaved Phased Array Receivers
9 Dec 21
A phased array receiver can include a plurality of antennas, a plurality of compound analog-to-digital converters and a beam former.
Cormac O'Sullivan, Benjamin Tardivel, João Marque
Filed: 24 Aug 21
Utility
Memory device with adaptive noise and voltage suppression during read-while-write operations
31 Aug 21
A selection circuit includes: a first selection device coupled between a write IO line and a first node; a second selection device coupled between a read IO line and a second node; a third selection device controllable by a first address decode signal, and coupled between a first bit line and a third node; a fourth selection device controllable by a second address decode signal, and coupled between a second bit line and the third node; a first suppression device controllable by a write enable signal, and coupled between the second node and ground; a second suppression device controllable by a read enable signal, and coupled between the first node and ground; a first isolation device controllable by the write enable signal, and coupled between the first and third nodes; and a second isolation device controllable by the read enable signal, and coupled between the second and third nodes.
John Dinh, Shane Hollmer
Filed: 10 Sep 19
Utility
Concurrent read and reconfigured write operations in a memory device
17 Aug 21
A method of controlling a memory device can include: receiving, by an interface, a write command from a host; beginning execution of a write operation on a first array plane of a memory array in response to the write command, where the memory array includes a plurality of memory cells arranged in a plurality of array planes; receiving, by the interface, a read command from the host; reconfiguring the write operation in response to detection of the read command during execution of the write operation; beginning execution of a read operation on a second array plane in response to the read command; and restoring the configuration of the write operation after the read operation has at least partially been executed.
Gideon Intrater, Bard Pedersen, Shane Hollmer, Derric Lewis, Stephen Trinh
Filed: 3 Mar 20
Utility
Nonvolatile memory devices, systems and methods with switching charge pump architectures
6 Jul 21
A memory device can include a plurality of banks, each bank including a memory cell array of nonvolatile (NV) memory cells; a plurality of charge pumps, including a first charge pump and second charge pump; and a switch circuit.
Stephen Trinh, Duong Vinh Hao, Nguyen Khac Hieu, Hendrik Hartono, John Dinh, Shane Charles Hollmer
Filed: 20 Jun 19
Utility
Memory device having programmable impedance elements with a common conductor formed below bit lines
6 Jul 21
An integrated circuit device can include a plurality of access transistors formed in a substrate having control terminals connected to word lines that extend in a first direction; a plurality of two-terminal programmable impedance elements formed over the substrate; at least one conductive plate structure formed on and having a common conductive connection to, the programmable impedance elements, and extending in at least the first direction; a plurality of storage contacts that extend from a first current terminal of each access transistor to one of the programmable impedance elements; a plurality of bit lines formed over the at least one conductive plate structure, the bit lines extending in a second direction different from the first direction; and a plurality of bit line contacts that extend from a second current terminal of each access transistor through openings in the at least one plate structure to one of the bit lines.
Mark T. Ramsbey, Venkatesh P. Gopinath, Jeffrey Allan Shields, Kuei Chang Tsai, Chakravarthy Gopalan, Michael A. Van Buskirk
Filed: 20 Jul 16
Utility
Integrated Module Assembly for Optical Integrated Circuits
10 Jun 21
An integrated module assembly can include: an optical integrated circuit having first and second optical devices; a PCB having first and second holes therein, where the optical integrated circuit is coupled upside down to a first side of the PCB; and first and second lenses coupled to a second side of the PCB, where the first and second sides of the PCB are opposite thereto; and where the first lens is in alignment with the first hole and the first optical device, and the second lens is in alignment with the second hole and the second optical device.
Bard M. Pedersen
Filed: 2 Dec 20
Utility
Apparatus and method for low-latency low-power analog-to-digital conversion with high input signals
8 Jun 21
Accordingly, embodiments of the present invention provide a method and apparatus for low-latency, low-power dissipation analog-to-digital conversion.
Joao Pedro Santos Cabrita Marques
Filed: 19 Feb 20
Utility
Standby Current Reduction In Memory Devices
27 May 21
A method of controlling a memory device can include: determining, by the memory device, a time duration in which the memory device is in a standby mode; automatically switching the memory device from the standby mode to a power down mode in response to the time duration exceeding a predetermined duration; exiting from the power down mode in response to signaling from a host device via an interface; and toggling a data strobe when data is ready to be output from the memory device in response to a read command from the host device.
Gideon Intrater
Filed: 28 Sep 20
Utility
Memory Device with Adaptive Noise and Voltage Suppression During Read-while-write Operations
11 Mar 21
A selection circuit includes: a first selection device coupled between a write IO line and a first node; a second selection device coupled between a read IO line and a second node; a third selection device controllable by a first address decode signal, and coupled between a first bit line and a third node; a fourth selection device controllable by a second address decode signal, and coupled between a second bit line and the third node; a first suppression device controllable by a write enable signal, and coupled between the second node and ground; a second suppression device controllable by a read enable signal, and coupled between the first node and ground; a first isolation device controllable by the write enable signal, and coupled between the first and third nodes; and a second isolation device controllable by the read enable signal, and coupled between the second and third nodes.
John Dinh, Shane Hollmer
Filed: 10 Sep 19
Utility
Static random access memories with programmable impedance elements and methods and devices including the same
14 Sep 20
An integrated circuit (IC) device can include static random access memory (SRAM) cells that each include a pair of latching devices, and first and second resistive elements disposed over the latching devices.
Venkatesh P. Gopinath, Nathan Gonzales
Filed: 11 Nov 18
Utility
Read latency reduction in a memory device
27 Jul 20
A memory device can include: a memory array with memory cells arranged as data lines; an interface that receives a read command requesting bytes of data in a consecutively addressed order from an address of a starting byte; a first buffer that stores a first data line from the memory array that includes the starting byte; a second buffer that stores a second data line from the memory array, which is consecutively addressed with respect to the first data line; output circuitry configured to access data from the buffers, and to sequentially output each byte from the starting byte through a highest addressed byte of the first data line, and each byte from a lowest addressed byte of the second data line until the requested data bytes has been output; and a data strobe driver that clocks each byte of data output by a data strobe on the interface.
Gideon Intrater, Bard Pedersen, Ishai Naveh
Filed: 11 Mar 19