106 patents
Utility
Semiconductor device including a superlattice and an asymmetric channel and related methods
9 Jan 24
A semiconductor device may include a substrate and spaced apart first and second doped regions in the substrate.
Hideki Takeuchi, Richard Burton, Yung-Hsuan Yang
Filed: 12 Apr 22
Utility
Methods for Making Semiconductor Devices with Superlattice and Embedded Quantum Dots
21 Dec 23
A method for making a semiconductor device may include forming at least one semiconductor layer including a superlattice therein.
MAREK HYTHA, NYLES WYNN CODY, ROBERT J. MEARS, HIDEKI TAKEUCHI, KEITH DORAN WEEKS
Filed: 21 Jun 23
Utility
Semiconductor Devices with Embedded Quantum Dots and Related Methods
21 Dec 23
A semiconductor device may include at least one semiconductor layer including a superlattice therein.
MAREK HYTHA, NYLES WYNN CODY, ROBERT J. MEARS, HIDEKI TAKEUCHI, KEITH DORAN WEEKS
Filed: 21 Jun 23
Utility
Method for making semiconductor device including superlattice with oxygen and carbon monolayers
19 Dec 23
A method for making a semiconductor device may include forming a superlattice adjacent a semiconductor layer.
Keith Doran Weeks, Nyles Wynn Cody, Marek Hytha, Robert J. Mears, Robert John Stephenson, Hideki Takeuchi
Filed: 30 Jun 21
Utility
Method for Making Semiconductor Device Including a Superlattice and Enriched Silicon 28 Epitaxial Layer
7 Dec 23
A method for making a semiconductor device may include forming a first single crystal silicon layer having a first percentage of silicon 28, and forming a superlattice above the first single crystal silicon layer.
MAREK HYTHA, KEITH DORAN WEEKS, NYLES WYNN CODY, HIDEKI TAKEUCHI
Filed: 23 Aug 23
Utility
Semiconductor device including superlattice with oxygen and carbon monolayers
5 Dec 23
A semiconductor device may include a semiconductor layer and a superlattice adjacent the semiconductor layer.
Keith Doran Weeks, Nyles Wynn Cody, Marek Hytha, Robert J. Mears, Robert John Stephenson, Hideki Takeuchi
Filed: 30 Jun 21
Utility
Semiconductor Device Including Superlattice with O18 Enriched Monolayers
9 Nov 23
A semiconductor device may include a semiconductor layer, and a superlattice adjacent the semiconductor layer and including stacked groups of layers.
MAREK HYTHA, NYLES WYNN CODY, KEITH DORAN WEEKS
Filed: 23 Jun 23
Utility
Dram Sense Amplifier Architecture with Reduced Power Consumption and Related Methods
9 Nov 23
A dynamic random access memory (DRAM) device may include an array of DRAM cells, with each DRAM cell configured to store a high logic voltage and a low logic voltage.
Richard Stephen Roy, Robert J. Mears
Filed: 3 May 23
Utility
Method for making semiconductor device including a superlattice and enriched silicon 28 epitaxial layer
7 Nov 23
A method for making a semiconductor device may include forming a first single crystal silicon layer having a first percentage of silicon 28, and forming a superlattice above the first single crystal silicon layer.
Marek Hytha, Keith Doran Weeks, Nyles Wynn Cody, Hideki Takeuchi
Filed: 21 Apr 21
Utility
Methods for Making Radio Frequency (RF) Semiconductor Devices Including a Ground Plane Layer Having a Superlattice
2 Nov 23
A method for making a radio frequency (RF) semiconductor device may include forming an RF ground plane layer on a semiconductor-on-insulator substrate and including a conductive superlattice.
HIDEKI TAKEUCHI, ROBERT J. MEARS
Filed: 22 Jun 23
Utility
Semiconductor device including superlattice with O
15 Aug 23
A semiconductor device may include a semiconductor layer, and a superlattice adjacent the semiconductor layer and including stacked groups of layers.
Marek Hytha, Nyles Wynn Cody, Keith Doran Weeks
Filed: 26 May 21
Utility
Method for making semiconductor device with selective etching of superlattice to accumulate non-semiconductor atoms
8 Aug 23
A method for making a semiconductor device may include forming a superlattice above a semiconductor layer, the superlattice including a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
Marek Hytha, Keith Doran Weeks, Nyles Wynn Cody
Filed: 28 Oct 21
Utility
Vertical semiconductor device with enhanced contact structure and associated methods
30 May 23
A vertical semiconductor device may include a semiconductor substrate having at least one trench therein, and a superlattice layer extending vertically adjacent the at least one trench.
Robert John Stephenson, Richard Burton, Dmitri Choutov, Nyles Wynn Cody, Daniel Connelly, Robert J. Mears, Erwin Trautmann
Filed: 23 May 22
Utility
Method for making an inverted T channel field effect transistor (ITFET) including a superlattice
30 May 23
A method for making a semiconductor device may include forming an inverted T channel on a substrate, with the inverted T channel comprising a superlattice.
Robert John Stephenson
Filed: 10 Apr 19
Utility
Method for Making Semiconductor Device with Selective Etching of Superlattice to Define Etch Stop Layer
4 May 23
A method for making a semiconductor device may include forming a superlattice above a semiconductor layer.
MAREK HYTHA, KEITH DORAN WEEKS, NYLES WYNN CODY
Filed: 28 Oct 21
Utility
Method for Making Semiconductor Device with Selective Etching of Superlattice to Accumulate Non-semiconductor Atoms
4 May 23
A method for making a semiconductor device may include forming a superlattice above a semiconductor layer, the superlattice including a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
MAREK HYTHA, KEITH DORAN WEEKS, NYLES WYNN CODY
Filed: 28 Oct 21
Utility
Gate-all-around (Gaa) Device Including a Superlattice
20 Apr 23
A semiconductor gate-all-around (GAA) device may include a semiconductor substrate, source and drain regions on the semiconductor substrate, a plurality of semiconductor nanostructures extending between the source and drain regions, and a gate surrounding the plurality of semiconductor nanostructures in a gate-all-around arrangement.
KEITH DORAN WEEKS, NYLES WYNN CODY, MAREK HYTHA, ROBERT J. MEARS, ROBERT JOHN STEPHENSON, HIDEKI TAKEUCHI
Filed: 21 Dec 22
Utility
Method for Making Gate-all-around (Gaa) Device Including a Superlattice
20 Apr 23
A method for making a semiconductor gate-all-around (GAA) device may include forming source and drain regions on a semiconductor substrate, forming a plurality of semiconductor nanostructures extending between the source and drain regions, and forming a gate surrounding the plurality of semiconductor nanostructures in a gate-all-around arrangement.
KEITH DORAN WEEKS, NYLES WYNN CODY, MAREK HYTHA, ROBERT J. MEARS, ROBERT JOHN STEPHENSON, HIDEKI TAKEUCHI
Filed: 21 Dec 22
Utility
Method for making semiconductor device with selective etching of superlattice to define etch stop layer
18 Apr 23
A method for making a semiconductor device may include forming a superlattice above a semiconductor layer.
Marek Hytha, Keith Doran Weeks, Nyles Wynn Cody
Filed: 28 Oct 21
Utility
Method for making semiconductor device including a superlattice and providing reduced gate leakage
31 Jan 23
A method for making a semiconductor device may include forming shallow trench isolation (STI) regions in a semiconductor substrate defining an active region therebetween in the semiconductor substrate and a pad oxide on the active region.
Hideki Takeuchi, Yung-Hsuan Yang
Filed: 11 Jun 20