Loading...
Docoh

Atomera (ATOM)

Utility
Semiconductor device including a superlattice and an asymmetric channel and related methods
10 May 22
A semiconductor device may include a substrate and spaced apart first and second doped regions in the substrate.
Hideki Takeuchi, Richard Burton, Yung-Hsuan Yang
Filed: 21 Apr 20
Utility
Method for Making a Semiconductor Device Using Superlattices with Different Non-semiconductor Thermal Stabilities
6 Jan 22
A method for making a semiconductor device may include forming first and second superlattices adjacent a semiconductor layer.
KEITH DORAN WEEKS, NYLES WYNN CODY, MAREK HYTHA, ROBERT J. MEARS
Filed: 1 Jul 21
Utility
Semiconductor Device Including Superlattice with Oxygen and Carbon Monolayers
6 Jan 22
A semiconductor device may include a semiconductor layer and a superlattice adjacent the semiconductor layer.
KEITH DORAN WEEKS, NYLES WYNN CODY, MAREK HYTHA, ROBERT J. MEARS, ROBERT JOHN STEPHENSON, HIDEKI TAKEUCHI
Filed: 30 Jun 21
Utility
Method for Making Semiconductor Device Including Superlattice with Oxygen and Carbon Monolayers
6 Jan 22
A method for making a semiconductor device may include forming a superlattice adjacent a semiconductor layer.
KEITH DORAN WEEKS, NYLES WYNN CODY, MAREK HYTHA, ROBERT J. MEARS, ROBERT JOHN STEPHENSON, HIDEKI TAKEUCHI
Filed: 30 Jun 21
Utility
Semiconductor Device Including a Superlattice and Providing Reduced Gate Leakage
16 Dec 21
A semiconductor device may include a semiconductor substrate, and shallow trench isolation (STI) regions in the semiconductor substrate defining an active region therebetween in the semiconductor substrate, with the active region having rounded shoulders adjacent the STI regions with an interior angle of at least 125°.
HIDEKI TAKEUCHI, Yung-Hsuan Yang
Filed: 11 Jun 20
Utility
Method for Making Semiconductor Device Including a Superlattice and Providing Reduced Gate Leakage
16 Dec 21
A method for making a semiconductor device may include forming shallow trench isolation (STI) regions in a semiconductor substrate defining an active region therebetween in the semiconductor substrate and a pad oxide on the active region.
Hideki Takeuchi, Yung-Hsuan Yang
Filed: 11 Jun 20
Utility
Semiconductor devices including hyper-abrupt junction region including spaced-apart superlattices and related methods
23 Nov 21
A semiconductor device may include a substrate and a hyper-abrupt junction region carried by the substrate.
Richard Burton, Marek Hytha, Robert J. Mears
Filed: 17 Jul 19
Utility
Semiconductor device including a superlattice with different non-semiconductor material monolayers
16 Nov 21
A semiconductor device may include a semiconductor substrate, and a superlattice on the semiconductor substrate and including a plurality of stacked groups of layers.
Keith Doran Weeks, Nyles Wynn Cody
Filed: 26 Feb 20
Utility
Semiconductor Device Including a Superlattice with Different Non-semiconductor Material Monolayers
26 Aug 21
A semiconductor device may include a semiconductor substrate, and a superlattice on the semiconductor substrate and including a plurality of stacked groups of layers.
KEITH DORAN WEEKS, Nyles Wynn Cody
Filed: 26 Feb 20
Utility
Method for Making Semiconductor Device Including a Superlattice with Different Non-semiconductor Material Monolayers
26 Aug 21
A method for making a semiconductor device may include forming a superlattice on a semiconductor substrate and including a plurality of stacked groups of layers.
Keith Doran Weeks, Nyles Wynn Cody
Filed: 26 Feb 20
Utility
Method for making a semiconductor device including a superlattice and an asymmetric channel and related methods
17 Aug 21
A method for making a semiconductor device may include forming spaced apart first and second doped regions in a substrate.
Hideki Takeuchi, Richard Burton, Yung-Hsuan Yang
Filed: 21 Apr 20
Utility
Method for making a semiconductor device including a superlattice within a recessed etch
27 Jul 21
A method for making a semiconductor device may include forming an isolation region adjacent an active region in a semiconductor substrate, and selectively etching the active region so that an upper surface of the active region is below an adjacent surface of the isolation region and defining a stepped edge therewith.
Nyles Wynn Cody, Keith Doran Weeks, Robert John Stephenson, Richard Burton, Yi-Ann Chen, Dmitri Choutov, Hideki Takeuchi, Yung-Hsuan Yang
Filed: 6 Mar 20
Utility
Methods for Making Bipolar Junction Transistors Including Emitter-base and Base-collector Superlattices
15 Jul 21
A method for making a bipolar junction transistor (BJT) may include forming a first superlattice on a substrate defining a collector region therein.
RICHARD BURTON
Filed: 26 Jun 20
Utility
Bipolar Junction Transistors Including Emitter-base and Base-collector Superlattices
15 Jul 21
A bipolar junction transistor (BJT) may include a substrate defining a collector region therein.
RICHARD BURTON
Filed: 26 Jun 20
Utility
Vertical Semiconductor Device with Enhanced Contact Structure and Associated Methods
11 Mar 21
A vertical semiconductor device may include a semiconductor substrate having at least one trench therein, and a superlattice liner at least partially covering sidewall portions of the at least one trench and defining a gap between opposing sidewall portions of the superlattice liner.
ROBERT JOHN STEPHENSON, RICHARD BURTON, DMITRI CHOUTOV, NYLES WYNN CODY, DANIEL CONNELLY, ROBERT J. MEARS, ERWIN TRAUTMANN
Filed: 23 Nov 20
Utility
Method for making semiconductor devices with hyper-abrupt junction region including spaced-apart superlattices
2 Mar 21
A method for making a semiconductor device may include forming a hyper-abrupt junction region above a substrate and including a first semiconductor layer having a first conductivity type, a first superlattice layer on the first semiconductor layer, a second semiconductor layer on the first superlattice layer and having a second conductivity type different than the first conductivity type, and a second superlattice layer on the second semiconductor layer.
Richard Burton, Marek Hytha, Robert J. Mears
Filed: 17 Jul 19
Utility
Method for making a varactor with a hyper-abrupt junction region including spaced-apart superlattices
2 Mar 21
A method for making a semiconductor device may include forming a hyper-abrupt junction region above a substrate and including a first semiconductor layer having a first conductivity type, a first superlattice layer on the first semiconductor layer, a second semiconductor layer on the first superlattice layer and having a second conductivity type different than the first conductivity type, and a second superlattice layer on the second semiconductor layer.
Richard Burton, Marek Hytha, Robert J. Mears
Filed: 17 Jul 19
Utility
Method for Making a Semiconductor Device Having a Hyper-abrupt Junction Region Including a Superlattice
21 Jan 21
A method for making semiconductor device may include forming a hyper-abrupt junction region on a substrate and including a first semiconductor layer having a first conductivity type, a superlattice layer on the first semiconductor layer, and a second semiconductor layer on the superlattice layer and having a second conductivity type different than the first conductivity type.
Richard Burton, Marek Hytha, Robert J. Mears
Filed: 17 Jul 19
Utility
Semiconductor Devices Including Hyper-abrupt Junction Region Including Spaced-apart Superlattices and Related Methods
21 Jan 21
A semiconductor device may include a substrate and a hyper-abrupt junction region carried by the substrate.
Richard Burton, Marek Hytha, Robert J. Mears
Filed: 17 Jul 19
Utility
Method for Making Semiconductor Devices with Hyper-abrupt Junction Region Including Spaced-apart Superlattices
21 Jan 21
A method for making a semiconductor device may include forming a hyper-abrupt junction region above a substrate and including a first semiconductor layer having a first conductivity type, a first superlattice layer on the first semiconductor layer, a second semiconductor layer on the first superlattice layer and having a second conductivity type different than the first conductivity type, and a second superlattice layer on the second semiconductor layer.
RICHARD BURTON, Marek Hytha, Robert J. Mears
Filed: 17 Jul 19
Patents are sorted by USPTO publication date, most recent first