52 patents
Utility
Methods for Making Semiconductor Devices with Superlattice and Embedded Quantum Dots
21 Dec 23
A method for making a semiconductor device may include forming at least one semiconductor layer including a superlattice therein.
MAREK HYTHA, NYLES WYNN CODY, ROBERT J. MEARS, HIDEKI TAKEUCHI, KEITH DORAN WEEKS
Filed: 21 Jun 23
Utility
Semiconductor Devices with Embedded Quantum Dots and Related Methods
21 Dec 23
A semiconductor device may include at least one semiconductor layer including a superlattice therein.
MAREK HYTHA, NYLES WYNN CODY, ROBERT J. MEARS, HIDEKI TAKEUCHI, KEITH DORAN WEEKS
Filed: 21 Jun 23
Utility
Method for Making Semiconductor Device Including a Superlattice and Enriched Silicon 28 Epitaxial Layer
7 Dec 23
A method for making a semiconductor device may include forming a first single crystal silicon layer having a first percentage of silicon 28, and forming a superlattice above the first single crystal silicon layer.
MAREK HYTHA, KEITH DORAN WEEKS, NYLES WYNN CODY, HIDEKI TAKEUCHI
Filed: 23 Aug 23
Utility
Semiconductor Device Including Superlattice with O18 Enriched Monolayers
9 Nov 23
A semiconductor device may include a semiconductor layer, and a superlattice adjacent the semiconductor layer and including stacked groups of layers.
MAREK HYTHA, NYLES WYNN CODY, KEITH DORAN WEEKS
Filed: 23 Jun 23
Utility
Dram Sense Amplifier Architecture with Reduced Power Consumption and Related Methods
9 Nov 23
A dynamic random access memory (DRAM) device may include an array of DRAM cells, with each DRAM cell configured to store a high logic voltage and a low logic voltage.
Richard Stephen Roy, Robert J. Mears
Filed: 3 May 23
Utility
Methods for Making Radio Frequency (RF) Semiconductor Devices Including a Ground Plane Layer Having a Superlattice
2 Nov 23
A method for making a radio frequency (RF) semiconductor device may include forming an RF ground plane layer on a semiconductor-on-insulator substrate and including a conductive superlattice.
HIDEKI TAKEUCHI, ROBERT J. MEARS
Filed: 22 Jun 23
Utility
Method for Making Semiconductor Device with Selective Etching of Superlattice to Define Etch Stop Layer
4 May 23
A method for making a semiconductor device may include forming a superlattice above a semiconductor layer.
MAREK HYTHA, KEITH DORAN WEEKS, NYLES WYNN CODY
Filed: 28 Oct 21
Utility
Method for Making Semiconductor Device with Selective Etching of Superlattice to Accumulate Non-semiconductor Atoms
4 May 23
A method for making a semiconductor device may include forming a superlattice above a semiconductor layer, the superlattice including a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
MAREK HYTHA, KEITH DORAN WEEKS, NYLES WYNN CODY
Filed: 28 Oct 21
Utility
Gate-all-around (Gaa) Device Including a Superlattice
20 Apr 23
A semiconductor gate-all-around (GAA) device may include a semiconductor substrate, source and drain regions on the semiconductor substrate, a plurality of semiconductor nanostructures extending between the source and drain regions, and a gate surrounding the plurality of semiconductor nanostructures in a gate-all-around arrangement.
KEITH DORAN WEEKS, NYLES WYNN CODY, MAREK HYTHA, ROBERT J. MEARS, ROBERT JOHN STEPHENSON, HIDEKI TAKEUCHI
Filed: 21 Dec 22
Utility
Method for Making Gate-all-around (Gaa) Device Including a Superlattice
20 Apr 23
A method for making a semiconductor gate-all-around (GAA) device may include forming source and drain regions on a semiconductor substrate, forming a plurality of semiconductor nanostructures extending between the source and drain regions, and forming a gate surrounding the plurality of semiconductor nanostructures in a gate-all-around arrangement.
KEITH DORAN WEEKS, NYLES WYNN CODY, MAREK HYTHA, ROBERT J. MEARS, ROBERT JOHN STEPHENSON, HIDEKI TAKEUCHI
Filed: 21 Dec 22
Utility
Semiconductor Device Including Superlattice with O18 Enriched Monolayers
1 Dec 22
A semiconductor device may include a semiconductor layer, and a superlattice adjacent the semiconductor layer and including stacked groups of layers.
Marek Hytha, Nyles Wynn Cody, Keith Doran Weeks
Filed: 26 May 21
Utility
Method for Making Semiconductor Device Including a Superlattice Providing Metal Work Function Tuning
1 Dec 22
A method for making a semiconductor gate-all-around (GAA) device may include forming source and drain regions on a semiconductor substrate, forming a plurality of semiconductor nanostructures extending between the source and drain regions, forming a gate surrounding the plurality of semiconductor nanostructures in a gate-all-around arrangement, and forming a dopant diffusion liner adjacent at least one of the source and drain regions and comprising a first superlattice.
ROBERT J. MEARS, HIDEKI TAKEUCHI
Filed: 18 May 22
Utility
Method for Making Semiconductor Device Including Superlattice with O18 Enriched Monolayers
1 Dec 22
A method for making a semiconductor device may include forming a semiconductor layer, and forming a superlattice adjacent the semiconductor layer and including stacked groups of layers.
MAREK HYTHA, Nyles Wynn Cody, Keith Doran Weeks
Filed: 26 May 21
Utility
Semiconductor Device Including a Superlattice Providing Metal Work Function Tuning
24 Nov 22
A semiconductor gate-all-around (GAA) device may include a semiconductor substrate, source and drain regions on the semiconductor substrate, a plurality of semiconductor nanostructures extending between the source and drain regions, a gate surrounding the plurality of semiconductor nanostructures in a gate-all-around arrangement, and a dopant diffusion liner adjacent at least one of the source and drain regions and comprising a first superlattice.
ROBERT J. MEARS, HIDEKI TAKEUCHI
Filed: 18 May 22
Utility
Methods for Making Bipolar Junction Transistors Including Emitter-base and Base-collector Superlattices
17 Nov 22
A method for making a bipolar junction transistor (BJT) may include forming a first superlattice on a substrate defining a collector region therein.
RICHARD BURTON
Filed: 26 Jul 22
Utility
Bipolar Junction Transistors Including Emitter-base and Base-collector Superlattices
17 Nov 22
A bipolar junction transistor (BJT) may include a substrate defining a collector region therein.
RICHARD BURTON
Filed: 26 Jul 22
Utility
Semiconductor Device Including a Superlattice and Enriched Silicon 28 Epitaxial Layer
3 Nov 22
A semiconductor device may include a first single crystal silicon layer having a first percentage of silicon 28; a second single crystal silicon layer having a second percentage of silicon 28 higher than the first percentage of silicon 28; and a superlattice between the first and second single crystal silicon layers.
MAREK HYTHA, KEITH DORAN WEEKS, NYLES WYNN CODY, HIDEKI TAKEUCHI
Filed: 21 Apr 21
Utility
Method for Making Semiconductor Device Including a Superlattice and Enriched Silicon 28 Epitaxial Layer
27 Oct 22
A method for making a semiconductor device may include forming a first single crystal silicon layer having a first percentage of silicon 28, and forming a superlattice above the first single crystal silicon layer.
MAREK HYTHA, KEITH DORAN WEEKS, NYLES WYNN CODY, HIDEKI TAKEUCHI
Filed: 21 Apr 21
Utility
Radio Frequency (RF) Semiconductor Devices Including a Ground Plane Layer Having a Superlattice
8 Sep 22
A radio frequency (RF) semiconductor device may include a semiconductor-on-insulator substrate, and an RF ground plane layer on the semiconductor-on-insulator substrate including a conductive superlattice.
HIDEKI TAKEUCHI, ROBERT J. MEARS
Filed: 3 Mar 22
Utility
Methods for Making Radio Frequency (RF) Semiconductor Devices Including a Ground Plane Layer Having a Superlattice
8 Sep 22
A method for making a radio frequency (RF) semiconductor device may include forming an RF ground plane layer on a semiconductor-on-insulator substrate and including a conductive superlattice.
Hideki Takeuchi, Robert J. Mears
Filed: 3 Mar 22