54 patents
Utility
Semiconductor device including a superlattice and an asymmetric channel and related methods
9 Jan 24
A semiconductor device may include a substrate and spaced apart first and second doped regions in the substrate.
Hideki Takeuchi, Richard Burton, Yung-Hsuan Yang
Filed: 12 Apr 22
Utility
Method for making semiconductor device including superlattice with oxygen and carbon monolayers
19 Dec 23
A method for making a semiconductor device may include forming a superlattice adjacent a semiconductor layer.
Keith Doran Weeks, Nyles Wynn Cody, Marek Hytha, Robert J. Mears, Robert John Stephenson, Hideki Takeuchi
Filed: 30 Jun 21
Utility
Semiconductor device including superlattice with oxygen and carbon monolayers
5 Dec 23
A semiconductor device may include a semiconductor layer and a superlattice adjacent the semiconductor layer.
Keith Doran Weeks, Nyles Wynn Cody, Marek Hytha, Robert J. Mears, Robert John Stephenson, Hideki Takeuchi
Filed: 30 Jun 21
Utility
Method for making semiconductor device including a superlattice and enriched silicon 28 epitaxial layer
7 Nov 23
A method for making a semiconductor device may include forming a first single crystal silicon layer having a first percentage of silicon 28, and forming a superlattice above the first single crystal silicon layer.
Marek Hytha, Keith Doran Weeks, Nyles Wynn Cody, Hideki Takeuchi
Filed: 21 Apr 21
Utility
Semiconductor device including superlattice with O
15 Aug 23
A semiconductor device may include a semiconductor layer, and a superlattice adjacent the semiconductor layer and including stacked groups of layers.
Marek Hytha, Nyles Wynn Cody, Keith Doran Weeks
Filed: 26 May 21
Utility
Method for making semiconductor device with selective etching of superlattice to accumulate non-semiconductor atoms
8 Aug 23
A method for making a semiconductor device may include forming a superlattice above a semiconductor layer, the superlattice including a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
Marek Hytha, Keith Doran Weeks, Nyles Wynn Cody
Filed: 28 Oct 21
Utility
Vertical semiconductor device with enhanced contact structure and associated methods
30 May 23
A vertical semiconductor device may include a semiconductor substrate having at least one trench therein, and a superlattice layer extending vertically adjacent the at least one trench.
Robert John Stephenson, Richard Burton, Dmitri Choutov, Nyles Wynn Cody, Daniel Connelly, Robert J. Mears, Erwin Trautmann
Filed: 23 May 22
Utility
Method for making an inverted T channel field effect transistor (ITFET) including a superlattice
30 May 23
A method for making a semiconductor device may include forming an inverted T channel on a substrate, with the inverted T channel comprising a superlattice.
Robert John Stephenson
Filed: 10 Apr 19
Utility
Method for making semiconductor device with selective etching of superlattice to define etch stop layer
18 Apr 23
A method for making a semiconductor device may include forming a superlattice above a semiconductor layer.
Marek Hytha, Keith Doran Weeks, Nyles Wynn Cody
Filed: 28 Oct 21
Utility
Method for making semiconductor device including a superlattice and providing reduced gate leakage
31 Jan 23
A method for making a semiconductor device may include forming shallow trench isolation (STI) regions in a semiconductor substrate defining an active region therebetween in the semiconductor substrate and a pad oxide on the active region.
Hideki Takeuchi, Yung-Hsuan Yang
Filed: 11 Jun 20
Utility
Semiconductor device including a superlattice and providing reduced gate leakage
11 Oct 22
A semiconductor device may include a semiconductor substrate, and shallow trench isolation (STI) regions in the semiconductor substrate defining an active region therebetween in the semiconductor substrate, with the active region having rounded shoulders adjacent the STI regions with an interior angle of at least 125°.
Hideki Takeuchi, Yung-Hsuan Yang
Filed: 11 Jun 20
Utility
Methods for making bipolar junction transistors including emitter-base and base-collector superlattices
6 Sep 22
A method for making a bipolar junction transistor (BJT) may include forming a first superlattice on a substrate defining a collector region therein.
Richard Burton
Filed: 26 Jun 20
Utility
Bipolar junction transistors including emitter-base and base-collector superlattices
6 Sep 22
A bipolar junction transistor (BJT) may include a substrate defining a collector region therein.
Richard Burton
Filed: 26 Jun 20
Utility
Method for making superlattice structures with reduced defect densities
30 Aug 22
A method for making a semiconductor device may include forming a superlattice on a substrate comprising a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
Keith Doran Weeks, Nyles Wynn Cody, Marek Hytha, Robert J. Mears, Robert John Stephenson
Filed: 14 Sep 20
Utility
Vertical semiconductor device with enhanced contact structure and associated methods
12 Jul 22
A vertical semiconductor device may include a semiconductor substrate having at least one trench therein, and a superlattice liner at least partially covering sidewall portions of the at least one trench and defining a gap between opposing sidewall portions of the superlattice liner.
Robert John Stephenson, Richard Burton, Dmitri Choutov, Nyles Wynn Cody, Daniel Connelly, Robert J. Mears, Erwin Trautmann
Filed: 23 Nov 20
Utility
Method for making semiconductor device including vertically integrated optical and electronic devices and comprising a superlattice
7 Jun 22
A method for making a semiconductor device may include forming a plurality of waveguides on a substrate, and forming a superlattice overlying the substrate and waveguides.
Robert John Stephenson
Filed: 10 Apr 19
Utility
Semiconductor device including a superlattice and an asymmetric channel and related methods
10 May 22
A semiconductor device may include a substrate and spaced apart first and second doped regions in the substrate.
Hideki Takeuchi, Richard Burton, Yung-Hsuan Yang
Filed: 21 Apr 20
Utility
Semiconductor devices including hyper-abrupt junction region including spaced-apart superlattices and related methods
23 Nov 21
A semiconductor device may include a substrate and a hyper-abrupt junction region carried by the substrate.
Richard Burton, Marek Hytha, Robert J. Mears
Filed: 17 Jul 19
Utility
Semiconductor device including a superlattice with different non-semiconductor material monolayers
16 Nov 21
A semiconductor device may include a semiconductor substrate, and a superlattice on the semiconductor substrate and including a plurality of stacked groups of layers.
Keith Doran Weeks, Nyles Wynn Cody
Filed: 26 Feb 20
Utility
Method for making a semiconductor device including a superlattice and an asymmetric channel and related methods
17 Aug 21
A method for making a semiconductor device may include forming spaced apart first and second doped regions in a substrate.
Hideki Takeuchi, Richard Burton, Yung-Hsuan Yang
Filed: 21 Apr 20