166 patents
Page 7 of 9
Utility
Magnetoresistive Structure Having Two Dielectric Layers, and Method of Manufacturing Same
10 Jun 20
A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers.
Sanjeev AGGARWAL, Kerry NAGEL, Jason Janesky
Filed: 18 Feb 20
Utility
Method of Manufacturing a Magnetoresistive Device
3 Jun 20
A magnetoresistive device may include an intermediate region positioned between a magnetically fixed region and a magnetically free region, and spin Hall channel region extending around a sidewall of at least the magnetically free region.
Sanjeev AGGARWAL, Sarin A. DESHPANDE
Filed: 25 Nov 19
Utility
Methods for monitoring and managing memory devices
18 May 20
The present disclosure is drawn to, among other things, a method of managing a memory device.
Kurt Baty, Terry Van Hulett
Filed: 20 Feb 18
Utility
Delayed write-back in memory
18 May 20
A memory having a delayed write-back to the array of data corresponding to a previously opened page allows delays associated with write-back operations to be avoided.
Thomas S. Andre, Syed M. Alam, Chitra K. Subramanian, Javed S. Barkatullah
Filed: 19 Mar 19
Utility
Feed forward bias system for MTJ voltage control
18 May 20
The present disclosure is drawn to, among other things, a magnetic memory.
Thomas Andre, Syed M. Alam, Frederick Neumeyer
Filed: 17 Jan 19
Utility
Method for magnetic device alignment on an integrated circuit
18 May 20
Techniques are presented for ensuring alignment marks are available for use and patterning magnetoresistive devices following the deposition of layers used to form the magnetoresistive devices.
Kerry Joseph Nagel
Filed: 9 Nov 17
Utility
Magnetoresistive stack/structure and method of manufacturing same
18 May 20
A method of manufacturing a magnetoresistive stack/structure comprising (a) etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer, (b) depositing a first encapsulation layer on the sidewalls of the second magnetic region and over a surface of the dielectric layer, (c) thereafter: (i) etching the first encapsulation layer which is disposed over the dielectric layer using a first etch process, and (ii) etching re-deposited material using a second etch process, wherein, after such etching, a portion of the first encapsulation layer remains on the sidewalls of the second magnetic region, (d) etching (i) through the dielectric layer to form a tunnel barrier and provide sidewalls thereof and (ii) etching the first magnetic region to provide sidewalls thereof, and (e) depositing a second encapsulation layer on the sidewalls of the tunnel barrier and first magnetic region.
Sarin A. Deshpande, Kerry Joseph Nagel, Chaitanya Mudivarthi, Sanjeev Aggarwal
Filed: 23 Sep 19
Utility
Preprogrammed data recovery
18 May 20
Techniques for recovering preprogrammed data from non-volatile memory are provided that include majority voting and/or use of one or more levels of ECC correction.
Sumio Ikegawa, Jon Slaughter
Filed: 18 Dec 17
Utility
Multiplexed memory in a communication processing system
11 May 20
In some examples, a communications device includes a magnetic memory accessible by both a central processing unit and a digital signal processor to enable the central processing unit to assist the digital signal processor in establishing and maintaining a communication channel.
Safdar Asghar
Filed: 17 Mar 19
Utility
Delayed write-back in memory with calibration support
11 May 20
A memory having a delayed write-back to the array of data corresponding to a previously opened page allows delays associated with write-back operations to be avoided.
Syed M. Alam
Filed: 26 Apr 17
Utility
Multilayer frame packages for integrated circuits having a magnetic shield integrated therein, and methods therefor
4 May 20
An integrated circuit package may comprise a multilayer frame package including: a bottom layer; and a magnetic shield layer, including a sub-frame and a magnetic shield disposed within a periphery of the sub-frame; and an integrated circuit die provided on or above the magnetic shield layer of the multilayer frame package.
Angelo V. Ugge
Filed: 5 Aug 18
Utility
Magnetic memory using spin-orbit torque
13 Apr 20
Spin-orbit-torque (SOT) segments are provided along the sides of free layers in magnetoresistive devices that include magnetic tunnel junctions.
Han-Jong Chia
Filed: 15 Nov 18
Utility
Magnetoresistive stacks and methods therefor
13 Apr 20
A magnetoresistive stack includes a seed region formed above a base region, a fixed magnetic region formed above the seed region and an intermediate region positioned between the fixed magnetic region and a free magnetic region.
Sumio Ikegawa, Jon Slaughter, Renu Whig
Filed: 1 Nov 18
Utility
Magnetoresistive stack and method of fabricating same
13 Apr 20
A magnetoresistive element (e.g., a spin-torque magnetoresistive memory element) includes a fixed magnetic layer, a free magnetic layer, having a high-iron alloy interface region located along a surface of the free magnetic layer, wherein the high-iron alloy interface region has at least 50% iron by atomic composition, and a first dielectric, disposed between the fixed magnetic layer and the free magnetic layer.
Renu Whig, Jijun Sun, Nicholas Rizzo, Jon Slaughter, Dimitri Houssameddine, Frederick Mancoff
Filed: 21 May 19
Utility
Short detection and inversion
6 Apr 20
In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on a state associated with one or more shorted bit cells.
Thomas Andre, Jon Slaughter, Dimitri Houssameddine, Syed M. Alam
Filed: 7 Jan 19
Utility
Magnetoresistive structure having two dielectric layers, and method of manufacturing same
30 Mar 20
A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers.
Sanjeev Aggarwal, Kerry Nagel, Jason Janesky
Filed: 23 Jan 19
Utility
Single-lock delay locked loop with cycle counter and method therefor
30 Mar 20
Once a delay locked loop has been locked to a clock signal, an omitted clock cycle is injected into the input of the delay locked loop without stopping the operation of the delay locked loop.
Jieming Qi, Aaron D. Willey
Filed: 14 Feb 19
Utility
ECC word configuration for system-level ECC compatibility
30 Mar 20
A memory device includes memory arrays configured to store pages of data organized into multiple ECC words.
Syed M. Alam, Thomas Andre
Filed: 27 Feb 19
Utility
Perpendicular magnetic memory using spin-orbit torque
23 Mar 20
Spin-orbit-torque (SOT) control strip lines are provided along the sides of free layers in perpendicular magnetic tunnel junction devices.
Sarin Deshpande, Sanjeev Aggarwal, Jason Janesky, Jon Slaughter, Phillip Lopresti
Filed: 10 Oct 18
Utility
Sensing Apparatus for Sensing Current Through a Conductor and Methods Therefor
11 Mar 20
A sensing apparatus for characterizing current flow through a conductor includes a plurality of magnetic sensors.
Angelo Ugge, Markus Schwickert, David Hayner
Filed: 12 Nov 19