89 patents
Page 5 of 5
Utility
Two layer quad bit error correction
9 Dec 19
In some examples, a memory device may be configured to provide quad bit error correction circuits.
Kurt Baty
Filed: 6 Sep 18
Utility
Magnetoresistive stack with seed region and method of manufacturing the same
18 Nov 19
A magnetoresistive stack/structure and method of manufacturing same comprising wherein the stack/structure includes a seed region, a fixed magnetic region disposed on and in contact with the seed region, a dielectric layer(s) disposed on the fixed magnetic region and a free magnetic region disposed on the dielectric layer(s).
Jijun Sun, Sanjeev Aggarwal, Han-Jong Chia, Jon M. Slaughter, Renu Whig
Filed: 18 Nov 18
Utility
Method of manufacturing a magnetoresistive stack/ structure using plurality of encapsulation layers
18 Nov 19
A method of manufacturing a magnetoresistive stack/structure comprising etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer; depositing a first encapsulation layer on the sidewalls of the second magnetic region and over the dielectric layer; etching the first encapsulation layer which is disposed over the exposed surface of the dielectric layer.
Kerry Joseph Nagel, Wenchin Lin, Sarin A. Deshpande, Jijun Sun, Sanjeev Aggarwal, Chaitanya Mudivarthi
Filed: 27 Oct 16
Utility
Self-referenced sense amplifier with precharge
11 Nov 19
Precharging circuits and techniques are presented for use with magnetic memory devices in order to speed up access to the memory cells for reading and writing.
Syed M. Alam, Chitra Subramanian
Filed: 4 Jun 18
Utility
Magnetoresistive stacks and methods therefor
11 Nov 19
A magnetoresistive device includes first and second ferromagnetic regions and an intermediate region formed of a dielectric material between the first and second ferromagnetic regions.
Jijun Sun
Filed: 18 Apr 18
Utility
Tuning magnetic anisotropy for spin-torque memory
28 Oct 19
Techniques for configuring the layers included in the free portion of a spin-torque magnetoresistive device are presented that allow for characteristics of the free portion to be tuned to meet the needs of various applications.
Han-Jong Chia, Jon Slaughter
Filed: 4 Feb 18
Utility
Magnetoresistive stack/structure and method of manufacturing same
28 Oct 19
A method of manufacturing a magnetoresistive stack/structure comprising (a) etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer, (b) depositing a first encapsulation layer on the sidewalls of the second magnetic region and over a surface of the dielectric layer, (c) thereafter: (i) etching the first encapsulation layer which is disposed over the dielectric layer using a first etch process, and (ii) etching re-deposited material using a second etch process, wherein, after such etching, a portion of the first encapsulation layer remains on the sidewalls of the second magnetic region, (d) etching (i) through the dielectric layer to form a tunnel barrier and provide sidewalls thereof and (ii) etching the first magnetic region to provide sidewalls thereof, and (e) depositing a second encapsulation layer on the sidewalls of the tunnel barrier and first magnetic region.
Sarin A. Deshpande, Kerry Joseph Nagel, Chaitanya Mudivarthi, Sanjeev Aggarwal
Filed: 30 Jul 18
Utility
Method of manufacturing integrated circuit using encapsulation during an etch process
28 Oct 19
A method of fabricating a magnetoresistive bit from a magnetoresistive stack includes etching through a first portion of the magnetoresistive stack using a first etch process to form one or more sidewalls.
Sanjeev Aggarwal, Sarin A. Deshpande, Kerry Joseph Nagel
Filed: 20 Aug 18
Utility
Bitline control in differential magnetic memory
14 Oct 19
The present disclosure is drawn to, among other things, a magnetoresistive memory.
Yaojun Zhang, Syed M. Alam, Thomas Andre
Filed: 15 May 18