2587 patents
Utility
Distribution of a Workload Among Nodes of a System with a Numa Architecture
18 Jan 24
Methods and systems are disclosed for distribution of a workload among nodes of a NUMA architecture.
Aditya Chatterjee
Filed: 12 Jul 22
Utility
Cost-saving Scheme for Scan Testing of 3D Stack Die
18 Jan 24
A system and method for efficiently routing scan data between two dies used in three-dimensional packaging are described.
SongGan Zang, Qi Shao, Lifeng Zhang, Ahmet Tokuz, Lu Lu
Filed: 15 Jul 22
Utility
Fanout Module Integrating a Photonic Integrated Circuit
18 Jan 24
A semiconductor package includes a first mold layer at least partially encasing at least one photonic integrated circuit.
BRETT P. WILKERSON, RAJA SWAMINATHAN, KONG TOON NG, RAHUL AGARWAL
Filed: 24 Jul 23
Utility
Coherent block read fulfillment
16 Jan 24
A coherent memory fabric includes a plurality of coherent master controllers and a coherent slave controller.
Vydhyanathan Kalyanasundharam, Amit P. Apte, Eric Christopher Morton, Ganesh Balakrishnan, Ann M. Ling
Filed: 21 Dec 21
Utility
Implementing heterogeneous wavefronts on a graphics processing unit (GPU)
16 Jan 24
Implementing heterogeneous wavefronts on a graphics processing unit (GPU) is disclosed.
Sooraj Puthoor, Bradford Beckmann, Nuwan Jayasena, Anthony Gutierrez
Filed: 28 Dec 20
Utility
Mechanism to efficiently rinse memory-side cache of dirty data
16 Jan 24
A method includes, in response to each write request of a plurality of write requests received at a memory-side cache device coupled with a memory device, writing payload data specified by the write request to the memory-side cache device, and when a first bandwidth availability condition is satisfied, performing a cache write-through by writing the payload data to the memory device, and recording an indication that the payload data written to the memory-side cache device matches the payload data written to the memory device.
Ravindra N. Bhargava, Ganesh Balakrishnan, Joe Sargunaraj, Chintan S. Patel, Girish Balaiah Aswathaiya, Vydhyanathan Kalyanasundharam
Filed: 24 Sep 20
Utility
Error detection and correction in memory modules using programmable ECC engines
16 Jan 24
A memory module includes one or more programmable ECC engines that may be programed by a host processing element with a particular ECC implementation.
Sudhanva Gurumurthi, Vilas Sridharan, Shaizeen Aga, Nuwan Jayasena, Michael Ignatowski, Shrikanth Ganapathy, John Kalamatianos
Filed: 25 Sep 20
Utility
Management of thrashing in a GPU
16 Jan 24
Systems, apparatuses, and methods for managing a number of wavefronts permitted to concurrently execute in a processing system.
Bradford Michael Beckmann, Steven Tony Tye, Brian L. Sumner, Nicolai Hähnle
Filed: 29 Dec 20
Utility
Variable tick for DRAM interface calibration
16 Jan 24
Methods and systems are disclosed for calibrating, by a memory interface system, an interface with dynamic random-access memory (DRAM) using a dynamically changing training clock.
Anwar Kashem, Craig Daniel Eaton, Pouya Najafi Ashtiani
Filed: 29 Dec 21
Utility
Graded throttling for network-on-chip traffic
16 Jan 24
Graded throttling for network-on-chip traffic, including: calculating, by an agent of a network-on-chip, a number of outstanding transactions issued by the agent; determining that the number of outstanding transactions meets a threshold; and implementing, by the agent, in response to the number of outstanding transactions meeting the threshold, a traffic throttling policy.
Narendra Kamat
Filed: 6 Oct 22
Utility
Overstress Design for Verification
11 Jan 24
Techniques for implementing an overstress design for verification that reduce production and verification time by enabling a verification system to perform verification of components of a circuit design selectively, accurately, and exhaustively under extreme stress scenarios are disclosed.
David Akselrod, Alexander Kaganov, David M. Dahle, Tyrone Huang
Filed: 11 Jul 22
Utility
Processing-in-memory concurrent processing system and method
9 Jan 24
A processing system includes a processing unit and a memory device.
Michael L. Chu, Ashwin Aji, Muhammad Amber Hassaan
Filed: 13 Sep 22
Utility
Using epoch counter values for controlling the retention of cache blocks in a cache
9 Jan 24
An electronic device includes a cache, a memory, and a controller.
Nuwan Jayasena
Filed: 30 Sep 21
Utility
Multi-adaptive cache replacement policy
9 Jan 24
Techniques for performing cache operations are provided.
John Kelley, Vanchinathan Venkataramani, Paul J. Moyer
Filed: 30 Sep 21
Utility
Provided inputs and provided output actions for use in platform management policies for platform management drivers
9 Jan 24
An electronic device includes a memory and a processor.
Alexander Sabino Duenas, Ashwini Chandrashekhara Holla, I-Cheng Chen, Xinzhe Li
Filed: 23 Dec 21
Utility
Processor-guided execution of offloaded instructions using fixed function operations
9 Jan 24
Processor-guided execution of offloaded instructions using fixed function operations is disclosed.
John Kalamatianos, Michael T. Clark, Marius Evers, William L. Walker, Paul Moyer, Jay Fleischman, Jagadish B. Kotra
Filed: 16 Dec 20
Utility
Shader source code performance prediction
9 Jan 24
Shader source code performance prediction is described.
Amit Ben-Moshe, Ian Charles Colbert
Filed: 8 Dec 21
Utility
Compacted addressing for transaction layer packets
9 Jan 24
Compacted addressing for transaction layer packets, including: determining, for a first epoch, one or more low entropy address bits in a plurality of first transaction layer packets; removing, from one or more memory addresses of one or more second transaction layer packets, the one or more low entropy address bits; and sending the one or more second transaction layer packets.
Ganesh Dasika, Sergey Blagodurov, Seyedmohammad Seyedzadehdelcheh
Filed: 23 Jul 20
Utility
Combined world-space pipeline shader stages
9 Jan 24
Improvements to graphics processing pipelines are disclosed.
Mangesh P. Nijasure, Randy W. Ramsey, Todd Martin
Filed: 19 Apr 21
Utility
Hardware assisted fine-grained data movement
9 Jan 24
A processor includes a task scheduling unit and a compute unit coupled to the task scheduling unit.
Muhammad Amber Hassaan, Anirudh Mohan Kaushik, Sooraj Puthoor, Gokul Subramanian Ravi, Bradford Beckmann, Ashwin Aji
Filed: 11 Jan 23