2587 patents
Page 3 of 130
Utility
Input/output Stutter Wake Alignment
4 Jan 24
An apparatus and method for efficiently performing power management for a multi-client computing system.
Indrani Paul, Alexander J. Branover, Benjamin Tsien, Elliot H. Mednick
Filed: 29 Jun 22
Utility
Data Encryption Suitable for Use In Systems with Processing-in-memory
4 Jan 24
An encryption circuit includes an iterative block cipher circuit.
Nuwan Jayasena, Shaizeen Dilawarhusen Aga, Vignesh Adhinarayanan
Filed: 29 Jun 22
Utility
Adaptive Power Throttling System
4 Jan 24
Systems, apparatuses, and methods for managing power allocation in a computing system.
Ashish Jain, Shang Yang, Arash Moghimi
Filed: 30 Jun 22
Utility
Scheduling Training of an Inter-chiplet Interface
4 Jan 24
Systems and methods are disclosed for scheduling a data link training by a controller.
Michael J. Tresidder, Benjamin Tsien
Filed: 29 Jun 22
Utility
Scalable Machine Check Architecture
4 Jan 24
An apparatus and method for supporting communication during error handling in a computing system.
Vilas K. Sridharan, Dean A. Liberty, Magiting Talisayon, Srikanth Masanam
Filed: 30 Jun 22
Utility
Droop Mitigation for an Inter-chiplet Interface
4 Jan 24
Systems and methods are disclosed for voltage droop mitigation associated with a voltage rail that supplies power to circuitry of a chiplet.
Michael J. Tresidder, Benjamin Tsien
Filed: 29 Jun 22
Utility
Remote Scalable Machine Check Architecture
4 Jan 24
An apparatus and method for supporting communication during error handling in a computing system.
Vilas K. Sridharan, Magiting Talisayon, Srikanth Masanam, Dean A. Liberty
Filed: 30 Jun 22
Utility
Channel and Sub-channel Throttling for Memory Controllers
4 Jan 24
An arbiter is operable to pick commands from a command queue for dispatch to a memory.
Kedarnath Balakrishnan, James R. Magro
Filed: 29 Jun 22
Utility
Allocating Memory for Processing-in-memory (Pim) Devices
4 Jan 24
Allocating memory for processing-in-memory (PIM) devices, including: allocating, in a first Dynamic Random Access Memory (DRAM) sub-array, a first data structure beginning in a first grain of the DRAM; allocating, in a second DRAM sub-array, a second data structure beginning in a second grain of the DRAM; and wherein the second DRAM sub-array is different from the first DRAM sub-array and the second grain is different from the first grain.
VIGNESH ADHINARAYANAN, MAHZABEEN ISLAM, JAGADISH B. KOTRA, SERGEY BLAGODUROV
Filed: 30 Jun 22
Utility
Automatic Provision of High Speed Serializer/deserializer Lanes by Firmware
4 Jan 24
Systems, apparatuses, and methods for automatic firmware provision of high speed serializer/deserializer (SERDES) links are disclosed.
George D. Azevedo, Peter Malcolm Barnes, Michael J. Tresidder
Filed: 30 Jun 22
Utility
Dynamic Topology Discovery and Management
4 Jan 24
An apparatus and method for efficiently supporting multiple peripheral communication protocols in a computing system.
Brian Mitchell, George D. Azevedo
Filed: 30 Jun 22
Utility
Through Silicon Via Macro with Dense Layout for Placement In an Integrated Circuit Floorplan
4 Jan 24
A system and method for efficiently designing a through silicon via (TSV) macro blocks are described.
Michael Edward Griffith, Aaron Keiichi Horiuchi, Donald A. Clay, Eric William Busta, Hye Jung Stanford, Kathryn E. Wilcox, Ruochen Xie, Russell Schreiber, Stephen J. Dussinger, William Edwin Laub, JR., Te-Hsuan Chen
Filed: 30 Jun 22
Utility
Communication of Data for a Model Between Nodes in an Electronic Device
4 Jan 24
An electronic device includes one or more data producing nodes and a data consuming node.
Kishore Punniyamurthy, Khaled Hamidouche, Brandon K. Potter, Rohit Shahaji Zambre
Filed: 29 Jun 22
Utility
Region-of-interest (Roi)-based Image Enhancement Using a Residual Network
4 Jan 24
Region-of-interest (ROI)-based image enhancement using a residual network, including: generating, based on an input image and a residual path of a residual network, a first output corresponding to a region-of-interest of the input image; generating, based on the input image and a skip path of the residual network, a second output; and generating an output image based on the first output and the second output.
TUNG CHUEN KWONG, YING LIU
Filed: 30 Jun 22
Utility
Hierarchical Depth Data Generation Using Primitive Fusion
4 Jan 24
Concurrently with performing a visibility pass to generate visibility data for two or more bins of an image, a processing system determines whether a primitive to be rendered covers at least a predetermined threshold percentage of a tile of the image.
Kiia K. Kallio, Jan Achrenius
Filed: 29 Jun 22
Utility
Pipeline Delay Reduction for Coarse Visibility Compression
4 Jan 24
A processing system divides an image to be rendered into one or more tiles and performs a visibility pass on the primitives of the image.
Kiia Kallio, Anton Palm
Filed: 30 Jun 22
Utility
LTH and SVLC Hybrid Core Architecture for Lower Cost Component Embedding In Package Substrate
4 Jan 24
An apparatus and method for efficiently transferring information as signals through a silicon package substrate.
Sriranga Sai Boyapati, Deepak Vasant Kulkarni, Rajasekaran Swaminathan
Filed: 30 Jun 22
Utility
Granular Clock Frequency Division Using Dithering Mechanism
4 Jan 24
An apparatus and method for efficiently generating clock signals.
Erwin Chi Wang Pang
Filed: 29 Jun 22
Utility
Automatic in-game subtitles and closed captions
2 Jan 24
An approach is provided for a gaming overlay application to provide automatic in-game subtitles and/or closed captions for video game applications.
Wei Liang, Ilia Blank, Patrick Fok, Le Zhang, Michael Schmit
Filed: 23 Dec 21
Utility
Clock frequency divider circuit
2 Jan 24
A system and method for efficiently generating clock signals are described.
Luke Jereme Whitaker, Edoardo Prete
Filed: 29 Oct 21