2587 patents
Page 8 of 130
Utility
Method for maintaining cache consistency during reordering
28 Nov 23
Systems, apparatuses, and methods for performing efficient data transfer in a computing system are disclosed.
Greggory D. Donley, Bryan P. Broussard
Filed: 3 Oct 18
Utility
Reducing latency in wireless virtual and augmented reality systems
28 Nov 23
Systems, apparatuses, and methods for reducing latency for wireless virtual and augmented reality applications are disclosed.
Mikhail Mironov, Gennadiy Kolesnik, Pavel Siniavine
Filed: 16 Jul 21
Utility
Video encoding/decoding using detected pattern of pixel intensity differences
28 Nov 23
Methods and apparatus encode image frames using intra-frame prediction by predicting pixels for a block of current pixels, based on a detected spatial pattern of pixel intensity differences among a plurality of neighboring reconstructed pixels to the block of current pixels, and encode a block of pixels of the image frame using the predicted block of reconstructed pixels.
Haibo Liu, Ihab Amer
Filed: 29 Mar 21
Utility
Pipeline Delay Elimination with Parallel Two Level Primitive Batch Binning
23 Nov 23
A technique for rendering is provided.
Michael John Livesley, Ruijin Wu
Filed: 13 Dec 22
Utility
Distributed Geometry
23 Nov 23
Systems, apparatuses, and methods for performing geometry work in parallel on multiple chiplets are disclosed.
Todd Martin, Tad Robert Litwiller, Nishank Pathak, Randy Wayne Ramsey
Filed: 1 Aug 23
Utility
Method And Apparatus For a Page-Local Delta-Based Prefetcher
23 Nov 23
A method includes recording a first set of consecutive memory access deltas, where each of the consecutive memory access deltas represents a difference between two memory addresses accessed by an application, updating values in a prefetch training table based on the first set of memory access deltas, and predicting one or more memory addresses for prefetching responsive to a second set of consecutive memory access deltas and based on values in the prefetch training table.
Susumu Mashimo, John Kalamatianos
Filed: 19 Apr 23
Utility
Address Translation Services Buffer
23 Nov 23
An address translation buffer or ATB is provided for emulating or implementing the PCIe (Peripheral Component Interface Express) ATS (Address Translation Services) protocol within a PCIe-compliant device.
Philip Ng, Vinay Patel
Filed: 31 Jul 23
Utility
Low power cache
21 Nov 23
A cache includes an upstream port, a cache memory for storing cache lines each having a line width, and a cache controller.
Vydhyanathan Kalyanasundharam, John Wuu, Chintan S. Patel
Filed: 20 Dec 21
Utility
Adaptive thread group dispatch
21 Nov 23
One or more shader processor inputs (SPIs) provide work items from a thread group for execution on one or more shader engines.
ZhongXiang Luo, JiXin Shan, MingTao Gu
Filed: 28 Dec 20
Utility
History-based selective cache line invalidation requests
21 Nov 23
Techniques for performing cache operations are provided.
Paul J. Moyer
Filed: 29 Oct 21
Utility
Performing store-to-load forwarding of a return address for a return instruction
21 Nov 23
A load/store unit includes a first queue including a first entry for a store operation and a second queue including a second entry for a load operation that includes a return instruction that redirects a program flow to a location indicated by the return instruction.
David Kaplan
Filed: 25 Jun 19
Utility
Texture decompression techniques
21 Nov 23
A method and computer processing system for performing texture compression comprising receiving, from a memory storing a compressed texture block and by a graphics processing unit including at least one rendering pipeline, the compressed texture block including two or more disjoint subsets, and decompressing, by the at least one rendering pipeline, the compressed texture block, wherein decompressing the compressed texture block comprises: decompressing data in the two or more disjoint subsets in the compressed texture block to form texels, wherein the two or more disjoint subsets include a first disjoint subset including a first set of color endpoints and a second disjoint subset including a second set of color endpoints.
Konstantine Iourcha, Andrew S. C. Pomianowski
Filed: 29 Oct 21
Utility
Sharing Package Pins In a Multi-chip Module (MCM)
16 Nov 23
A semiconductor package includes multiple dies that share the same package pin.
YULEI SHEN, TYRONE TUNG HUANG, CHEN-KUAN HONG
Filed: 13 May 22
Utility
Memory Calibration System and Method
16 Nov 23
A method for performing stutter of dynamic random access memory (DRAM) where a system on a chip (SOC) initiates bursts of requests to the DRAM to fill buffers to allow the DRAM to self-refresh is disclosed.
Jing Wang, Kedarnath Balakrishnan, Kevin M. Brandl, James R. Magro
Filed: 17 May 23
Utility
Apparatus and method for providing subsystem processor based power shifting for peripheral devices
14 Nov 23
A computing device and method controls power consumption of a graphics processing unit in the computing device by the GPU determining an allocated power for the USB device connected through a USB port, such as a USB-C port.
Vincent Cueva, Gia Tung Phan
Filed: 26 Jul 21
Utility
Error handling for resilient software
14 Nov 23
Error handling for resilient software includes: receiving data indicating a region of resilient memory; detecting an error associated with a region of memory; and preventing raising an exception for the error in response to the region of memory falling within the region of resilient memory by preventing the region of memory as being identified as including the error.
Sudhanva Gurumurthi, Vilas Sridharan
Filed: 10 Jan 22
Utility
Automatic triggering of a gameplay recording using visual and acoustic fingerprints
14 Nov 23
Systems and methods are disclosed that automatically generating a gameplay recording from an application.
Wei Liang, Le Zhang, Ilia Blank, Patrick Pak Kin Fok
Filed: 3 Sep 21
Utility
Enhanced page information co-processor
14 Nov 23
A processing system includes a primary processor and a co-processor.
Steven Raasch, Andrew G. Kegel
Filed: 12 Dec 19
Utility
Spatial hashing for world-space spatiotemporal reservoir re-use for ray tracing
14 Nov 23
A processor shares path tracing data across sampling locations to amortize computations across space and time.
Guillaume Marie Boisse
Filed: 22 Jun 21
Utility
Real-time low latency computer vision/machine learning compute accelerator with smart convolutional neural network scheduler
14 Nov 23
Methods and devices are provided for processing image data on a sub-frame portion basis using layers of a convolutional neural network.
Tung Chuen Kwong, David Porpino Sobreira Marques, King Chiu Tam, Shilpa Rajagopalan, Benjamin Koon Pan Chan, Vickie Youmin Wu
Filed: 30 Dec 20