16605 patents
Page 6 of 831
Utility
Memory systems for secure sequential storage devices
9 Jan 24
Methods, systems, and devices for memory systems for secure sequential storage devices are described.
Zoltan Szubbocsev
Filed: 28 Jan 22
Utility
Row hammer attack alert
9 Jan 24
An apparatus having counters for sub-addresses in segments of row address to count activation commands applied to row addresses including the sub-addresses.
Kai Wang
Filed: 17 May 22
Utility
Inter-memory movement in a multi-memory system
9 Jan 24
Methods, systems, and devices for improved inter-memory movement in a multi-memory system are described.
Sourabh Dhir, Kang-Yong Kim
Filed: 11 Sep 20
Utility
Managing trim commands in a memory sub-system
9 Jan 24
Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include receiving, by the processing device, a trim command on the memory device, wherein the trim command references a range of logical block addresses (LBAs).
Yueh-Hung Chen, Fangfang Zhu, Horia Simionescu, Chih-Kuo Kao, Jiangli Zhu
Filed: 31 Aug 21
Utility
Apparatus with combinational access mechanism and methods for operating the same
9 Jan 24
Methods, apparatuses, and systems related to combining and utilizing multiple memory circuits having complementary characteristics are described.
Hyun Yoo Lee, Kang-Yong Kim
Filed: 11 May 22
Utility
Memory devices with cryptographic components
9 Jan 24
An apparatus, such as a memory system (e.g., a NAND memory system), can have a controller with a first error correction code component and a memory device (e.g., a NAND memory device) coupled to the controller.
Antonino Mondello, Carmelo Condemi, Francesco Tomaiuolo, Tommaso Zerilli
Filed: 28 Nov 22
Utility
Background memory scan block selection
9 Jan 24
The memory sub-systems of the present disclosure selects, for memory scans, a memory block which has a highest page fill ratio.
Alex J. Wesenberg, Johnny A. Lam, Michael Winterfeld
Filed: 16 Dec 20
Utility
Memory sub-system for performing wear-leveling adjustments based on memory component endurance estimations
9 Jan 24
A system comprising a memory component including blocks, and a processing device, operatively coupled with the memory component.
Zoltan Szubbocsev
Filed: 7 Oct 22
Utility
Message routing in a network-ready storage product for internal and external processing
9 Jan 24
A storage product having a network interface and a bus switch connecting a random-access memory, a processing device, and a storage device, and connected via an external computer bus to an external processor.
Luca Bert
Filed: 15 Jul 22
Utility
System for predicting properties of structures, imager system, and related methods
9 Jan 24
A method of predicting virtual metrology data for a wafer lot that includes receiving first image data from an imager system, the first image data relating to at least one first wafer lot, receiving measured metrology data from metrology equipment relating to the at least one first wafer lot, applying one or more machine learning techniques to the first image data and the measured metrology data to generate at least one predictive model for predicting at least one of virtual metrology data or virtual cell metrics data of wafer lots, and utilizing the at least one generated predictive model to generate at least one of first virtual metrology data or first virtual cell metrics data for the first wafer lot.
Amitava Majumdar, Qianlan Liu, Pradeep Ramachandran, Shawn D. Lyonsmith, Steve K. McCandless, Ted L. Taylor, Ahmed N. Noemaun, Gordon A. Haller
Filed: 10 Dec 20
Utility
Read algorithm for memory device
9 Jan 24
Methods, systems, and devices for a read algorithm for a memory device are described.
Ferdinando Bedeschi, Umberto Di Vincenzo, Riccardo Muzzetto
Filed: 17 Nov 22
Utility
Apparatuses, systems, and methods for counter-based read clock in stacked memory devices
9 Jan 24
Apparatuses, systems, and methods for counter based read clocks in stacked memory devices.
Tomohiko Yamagishi, Seiji Narui, Kiyoshi Nakai, Takamasa Suzuki
Filed: 30 Dec 21
Utility
Content addressable memory systems with content addressable memory buffers
9 Jan 24
An apparatus (e.g., a content addressable memory system) can have a controller; a first content addressable memory coupled to the controller and a second content addressable memory coupled to the controller.
Ameen D. Akel, Sean S. Eilert
Filed: 1 Mar 21
Utility
Adjusting pass-through voltage based on threshold voltage shift
9 Jan 24
Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device.
Kishore Kumar Muchherla, Mustafa N. Kaynak, Sampath K Ratnam, Peter Feeley, Sivagnanam Parthasarathy
Filed: 17 Aug 22
Utility
Memory sub-system including an in-package sequencer to perform error correction and memory testing operations
9 Jan 24
A sequencer component residing in a first package receives data from a controller residing in a second package that is different than the first package including the sequencer component.
Samir Mittal, Ying Yu Tai, Cheng Yuan Wu, Jiangli Zhu
Filed: 16 Apr 21
Utility
Methods of cooling semiconductor devices
9 Jan 24
Some embodiments include methods of forming voids within semiconductor constructions.
David H. Wells
Filed: 2 May 22
Utility
Microelectronic components including metal pillars secured to bond pads, and related methods, assemblies, and systems
9 Jan 24
A microelectronic component comprises a substrate having at least one bond pad on a surface thereof and a metal pillar structure on the at least one bond pad, the metal pillar structure comprising a metal pillar on the at least one bond pad and a solder material having a portion within a reservoir within the metal pillar and another portion protruding from an end of the metal pillar opposite the at least one bond pad.
Shams U. Arifeen, Christopher Glancey, Koustav Sinha
Filed: 4 Mar 22
Utility
Three-state programming of memory cells
9 Jan 24
The present disclosure includes apparatuses, methods, and systems for three-state programming of memory cells.
Hernan A Castro, Jeremy M. Hirst, Shanky K. Jain, Richard K. Dodge, William A. Melton
Filed: 22 Apr 22
Utility
Memory devices including gate leakage transistors
9 Jan 24
A memory device includes a string of series-connected memory cells, a data line, a first select transistor, a common source, a second select transistor, and a gate leakage transistor.
Andrew Bicksler, Marc Aoulaiche
Filed: 27 Aug 21
Utility
NAND data placement schema
9 Jan 24
Carminantonio Manganelli, Paolo Papa, Massimo Iaculo, Giuseppe D'Eliseo, Alberto Sassara
Filed: 5 Dec 22