7776 patents
Utility
Reticle constructions and photo-processing methods
16 Jan 24
Some embodiments include a reticle which includes first pattern features and second pattern features.
Chung-Yi Lee, Reha M. Bafrali
Filed: 28 Jan 21
Utility
Log compression
16 Jan 24
Systems, apparatuses, and methods related log compression are described.
Reshmi Basu, Libo Wang
Filed: 17 Oct 22
Utility
Maintaining data consistency in a memory sub-system that uses hybrid wear leveling operations
16 Jan 24
A processing device in a memory sub-system maintains a mapping data structure to track data movements from a plurality of data management units associated with a media management operation on a memory device.
Ning Chen, Jiangli Zhu, Ying Yu Tai
Filed: 18 Mar 22
Utility
Scheduling of read operations and write operations based on a data bus mode
16 Jan 24
A data bus is determined to be in a write mode.
Wei Wang, Jiangli Zhu, Ying Yu Tai, Samir Mittal
Filed: 4 Dec 20
Utility
Instructive actions based on categorization of input data
16 Jan 24
Systems, devices, and methods related to generating instructive actions based on categorization of input data are described.
Carla L. Christensen, Lavanya Sriram, Swetha Barkam, Anshika Sharma, Libo Wang
Filed: 28 Aug 20
Utility
Integrated circuit device with deep learning accelerator and random access memory
16 Jan 24
Systems, devices, and methods related to a Deep Learning Accelerator and memory are described.
Poorna Kale, Jaime Cummins
Filed: 9 Apr 20
Utility
Displaying augmented reality responsive to an input
16 Jan 24
Methods, devices, and systems related to a computing device for displaying an AR responsive to an input are described.
Radhika Viswanathan, Bhumika Chhabra, Carla L. Christensen, Zahra Hosseinimakarem
Filed: 10 Jan 23
Utility
Temperature-based scrambling for error control in memory systems
16 Jan 24
Methods, systems, and devices for temperature-based scrambling for error control in memory systems are described.
Christopher Joseph Bueb
Filed: 30 Nov 21
Utility
Enhanced write performance utilizing program interleave
16 Jan 24
A system includes a memory sub-system including a single-level cell (SLC) cache, a first multiple level cell (XLC) storage including a first XLC block, and a second XLC storage including a second XLC block.
Daniel J. Hubbard, Roy Leonard
Filed: 22 Apr 22
Utility
Converting floating-point bit strings in a multi-user network
16 Jan 24
Systems, apparatuses, and methods related to arithmetic and logical operations in a multi-user network are described.
Vijay S. Ramesh
Filed: 25 Mar 21
Utility
Optimization of soft bit windows based on signal and noise characteristics of memory cells
16 Jan 24
A memory device to determine a voltage window to read soft bit data.
James Fitzpatrick, Sivagnanam Parthasarathy, Patrick Robert Khayat, AbdelHakim S. Alhussien
Filed: 24 Nov 21
Utility
Memory true erase with pulse steps to facilitate erase suspend
16 Jan 24
A memory device includes a memory array of memory cells and control logic operatively coupled to the memory array.
Tomoharu Tanaka
Filed: 1 Feb 22
Utility
Memory devices for comparing input data to data stored in memory cells coupled to a data line
16 Jan 24
A memory device might include control circuitry configured to cause the memory device to compare input data to data stored in memory cells connected to a data line, cause a first level of current to flow from the data line in response to a mismatch between one digit of the input data and data stored in a respective pair of memory cells, cause a second level of current to flow from the data line in response to a mismatch between a different digit of the input data and the data stored in a respective pair of memory cells, compare a representation of a level of current in the data line to a reference, and deem the input data to potentially match or not match the data stored in the plurality of memory cells in response to the comparison.
Kenneth J. Eldredge, Frankie F. Roohparvar, Luca De Santis, Tommaso Vali
Filed: 2 Mar 21
Utility
Memory cell sensing
16 Jan 24
Sensing devices might include a first voltage node configured to receive a first voltage level, a second voltage node configured to receive a second voltage level lower than the first voltage level, a p-type field-effect transistor (pFET) selectively connected to a data line, and a sense node selectively connected to the pFET.
Chang H. Siau, Hao T. Nguyen
Filed: 4 Nov 22
Utility
Select gate reliability
16 Jan 24
A method includes determining a programmed threshold voltage for a select gate of a memory string and assigning the select gate a programmed reliability rank based upon the programmed threshold voltage.
Falgun G. Trivedi
Filed: 11 Feb 22
Utility
Memory programming methods and memory systems
16 Jan 24
Memory programming methods and memory systems are described.
Takafumi Kunihiro
Filed: 24 Sep 19
Utility
Weighted wear leveling for improving uniformity
16 Jan 24
A memory device can include multiple memory cells and a processing device operatively coupled with the memory device to perform operations including grouping the memory cells into a groups based on a metric reflecting an electrical distance of a memory cell from a voltage source, and determining, for each group, a respective share of write operations, wherein the share of write operations is related to an aggregate value of the metric for memory cells of the group.
Zhongyuan Lu, Karthik Sarpatwari, Nevil N. Gajera
Filed: 8 Dec 21
Utility
Quick reliability scan for memory device
16 Jan 24
Technologies for performing a quick reliability scan include, for a particular block of a set of blocks of different block types, each block of the set of blocks including pages of memory of a physical memory device, identifying subset of the pages of the block.
Saeed Sharifi Tehrani, Vamsi Pavan Rayaprolu
Filed: 6 Dec 22
Utility
Capacitive units and methods of forming capacitive units
16 Jan 24
Some embodiments include a capacitive unit having two or more capacitive tiers.
Yuichi Yokoyama
Filed: 12 Apr 21
Utility
Microelectronic devices having features with a fin portion of different sidewall slope than a lower portion, and related methods and electronic systems
16 Jan 24
A method of forming a microelectronic device structure comprises exposing a silicon structure to an etching chemistry at a first bias voltage of greater than about 500 V to form at least one initial trench between sidewalls of features formed in the silicon structure.
Yan Li, Song Guo, Mohd Kamran Akhtar, Alex J. Schrinsky
Filed: 9 Jul 20