467 patents
Page 3 of 24
Utility
Digital phase-locked loop circuit
12 Sep 23
In some examples, a digital phase-locked loop (PLL) circuit can include a switch to provide a reference input signal having a first frequency in response to an output signal having a second frequency that is greater than the first frequency.
Vineeth Anavangot, Riju Biswas
Filed: 11 Mar 22
Utility
Converting analog variable delay in real number modeling code to cycle-driven simulation interface code
5 Sep 23
A method and a system for converting a variable delay in real number modeling code to cycle-driven simulation interface event for digital/mixed signal emulation is provided.
Ophir Turbovich, Yosinori Watanabe
Filed: 28 Sep 17
Utility
System and method for glitch power estimation
5 Sep 23
Embodiments include herein are directed towards a system and method for estimating glitch power associated with an emulation process is provided.
Steev Wilcox, Daniel Fernandes
Filed: 11 Jan 22
Utility
Digitally-controlled quadrature correction loop
22 Aug 23
A method and system for performing a duty cycle correction and quadrature error correction for a quarter-rate architecture TX/RX communication system, including correcting a duty cycle error between a first clock signal and a second clock signal, and correcting a quadrature error between a third clock signal and a fourth clock signal.
Rania Hassan Abdellatif Abdelrahim Mekky, Jean-Francois Delage, Guillaume Fortin
Filed: 9 Jul 21
Utility
Routing congestion based on fractional via cost and via density
22 Aug 23
Various embodiments provide for routing a circuit design using routing congestion based on fractional via cost, via density, or both in view of one or more design rules.
Gracieli Posser, Derong Liu, Mehmet Can Yildiz, Zhuo Li
Filed: 7 May 21
Utility
Method and system for saving and restoring of initialization actions on dut and corresponding test environment
8 Aug 23
A computer implemented method may include executing a first simulation test for testing a device under test (DUT) and a corresponding test environment; saving a snapshot image of the DUT and of the corresponding test environment upon completion of initialization actions included in the first simulation test to configure the DUT; compiling a DUT part of a second simulation test into the saved snapshot image of the DUT to obtain a restore image for the DUT; loading the restore image of the DUT and restoring the snapshot image of the test environment; loading a test environment part of the second simulation test; and executing the second simulation test on the DUT and corresponding test environment.
Tirumala Surya Prasad Annepu, Shai Fuss, Zeev Kirshenbaum
Filed: 22 Oct 20
Utility
System and method for memory management
8 Aug 23
Embodiments include herein are directed towards a double data rate (“DDR”) controller system.
John Michael MacLaren
Filed: 29 Nov 21
Utility
Device and method for low-latency and encrypted hardware layer communication
8 Aug 23
A method of low-latency and encrypted hardware layer communication includes calculating, by an encryption circuit of a communication bridge controller, a pre-calculated encryption keys corresponding to a block encryptor of the encryption circuit, each block encryptor configured to use a corresponding pre-calculated encryption key to encrypt a corresponding unencrypted data block of a data transmission having one or more unencrypted data blocks, storing the one or more pre-calculated encryption keys in an encryption key memory associated with the communication bridge, for each unecrypted data block, encrypting the unencrypted data block using the corresponding pre-calculated encryption key to generate an encrypted data block and an authentication code block for the unencrypted data block, aggregating one or more encrypted data blocks into an encrypted data transmission, and generating an authenticated code corresponding to the encrypted data transmission based upon each of the authentication code blocks of each of the encrypted data blocks.
Steven Ho, Gopi Krishnamurthy, Anish Mathew
Filed: 11 Aug 21
Utility
System and method for consolidating and applying manufacturing constraints
1 Aug 23
The present disclosure relates to a system and method for use in an electronic circuit design.
Utpal Bhattacharyya, Randall Scott Lawson, Edward Brian Acheson, Amit Sharma
Filed: 28 Jan 21
Utility
Method, product, and apparatus for a multidimensional processing array for hardware acceleration of convolutional neural network inference
27 Jun 23
An approach includes receiving a machine learning processing job, executing the machine learning processing job using parallel processing of multiple output pixels each cycle by walking data across processing elements with broadcast weights within regions and executing parallel multiplication operations, and generating an output indicating whether the machine learning processing job was successful or failed.
Ngai Ngai William Hung, Dhiraj Goswami, Michael Patrick Zimmer, Yong Liu
Filed: 30 Jun 20
Utility
Method, product, and system for automated, guided, and region-based layer density balancing
27 Jun 23
An approach is disclosed herein for balancing layer densities in using an automated process.
Yu-Chen Lin, Yi-Ning Chang, Tyler James Lockman
Filed: 31 Mar 21
Utility
System and method for memory management
30 May 23
Embodiments include herein are directed towards a dynamic random access memory system.
John Michael MacLaren, Thomas Joseph Shepherd, Davika Raghu
Filed: 15 Nov 21
Utility
Removal of dependent instructions from an execution pipeline
23 May 23
Techniques are disclosed relating to an apparatus, including a data storage circuit having a plurality of entries, and a load-store pipeline configured to allocate an entry in the data storage circuit in response to a determination that a first instruction includes an access to an external memory circuit.
Robert T. Golla, Deepak Panwar
Filed: 10 Feb 21
Utility
Method, product, and apparatus for a machine learning process using dynamic rearrangement of sparse data and corresponding weights
16 May 23
An approach is described for a method, product, and apparatus for a machine learning process using dynamic rearrangement of sparse data and corresponding weights.
Yong Liu, Ngai Ngai William Hung, Michael Patrick Zimmer
Filed: 30 Jun 20
Utility
Machine-learning based clustering for clock tree synthesis
9 May 23
Aspects of the present disclosure address systems and methods for performing a machine-learning based clustering of clock sinks during clock tree synthesis.
Bentian Jiang, Natarajan Viswanathan, Zhuo Li, Yi-Xiao Ding
Filed: 31 Dec 20
Utility
Programmable fractional ripple divider
18 Apr 23
Embodiments included herein are directed towards a fractional feedback divider circuit and associated method.
Sudipta Sarkar, Dimitrios Loizos, Mehran Mohammadi Izad, Paul Lee, Steven Elliott Mikes, Manohar Bhavsar Nagaraju
Filed: 25 Apr 22
Utility
Constraint-based dynamic quantization adjustment for fixed-point processing
18 Apr 23
Aspects of the present disclosure address systems and methods for fixed-point quantization using a dynamic quantization level adjustment scheme.
Ming Kai Hsu, Sandip Parikh
Filed: 14 Sep 18
Utility
Failure mode analysis for circuit design
18 Apr 23
Various embodiments provide for failure mode analysis of a circuit design, which can be used as part of electronic design automation (EDA).
Stefano Lorenzini, Antonino Armato
Filed: 4 Nov 19
Utility
High speed differential input single phase clock flip-flop
11 Apr 23
The present disclosure relates to a high speed, differential input, single phase clock circuit.
Rajendra Singh Shahi
Filed: 13 Jul 21
Utility
Partitioned UFP for displayport repeater
4 Apr 23
Methods and systems are disclosed for an upstream facing port implementation for DisplayPort link-training tunable PHY repeaters (LTTPRs).
Yao Luo
Filed: 24 May 21