291 patents
Utility
Adaptive bias decoder to provide a voltage to a control gate line in an analog neural memory array in artificial neural network
16 Jan 24
Numerous embodiments of analog neural memory arrays are disclosed.
Hieu Van Tran, Thuan Vu, Stanley Hong, Stephen Trinh, Anh Ly, Nhan Do, Mark Reiten
Filed: 4 Jan 21
Utility
Virtual ground non-volatile memory array
19 Dec 23
A memory device with memory cell pairs each having a single continuous channel region, first and second floating gates over first and second portions of the channel region, an erase gate over a third portion of the channel region between the first and second channel region portions, and first and second control gates over the first and second floating gates.
Hieu Van Tran, Hung Quoc Nguyen, Nhan Do
Filed: 21 Jun 22
Utility
Precise data tuning method and apparatus for analog neural memory in an artificial neural network
19 Dec 23
Numerous examples of a precision programming apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network.
Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
Filed: 27 Jul 22
Utility
Compensation for reference transistors and memory cells in analog neuro memory in deep learning artificial neural network
19 Dec 23
Numerous embodiments are disclosed for compensating for differences in the slope of the current-voltage characteristic curve among reference transistors, reference memory cells, and flash memory cells during a read operation in an analog neural memory in a deep learning artificial neural network.
Hieu Van Tran, Vipin Tiwari, Nhan Do
Filed: 10 Aug 22
Utility
Verification of a weight stored in a non-volatile memory cell in a neural network following a programming operation
28 Nov 23
Numerous embodiments are disclosed for verifying a weight programmed into a selected non-volatile memory cell in a neural memory.
Farnood Merrikh Bayat, Xinjie Guo, Dmitri Strukov, Nhan Do, Hieu Van Tran, Vipin Tiwari, Mark Reiten
Filed: 16 Apr 21
Utility
Programming of a Selected Non-volatile Memory Cell
16 Nov 23
In one example, a method comprises performing a first programming process on a selected non-volatile memory cell, the first programming process comprising a plurality of program-verify cycles, wherein a programming voltage duration of increasing period is applied to one of a floating gate, a control gate terminal, an erase gate terminal, and a source line terminal of the selected non-volatile memory cell in each program-verify cycle after the first program-verify cycle.
Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
Filed: 27 Jul 23
Utility
Compensation for reference transistors and memory cells in analog neuro memory in deep learning artificial neural network
24 Oct 23
Numerous embodiments are disclosed for compensating for differences in the slope of the current-voltage characteristic curve among reference transistors, reference memory cells, and flash memory cells during a read operation in an analog neural memory in a deep learning artificial neural network.
Hieu Van Tran, Vipin Tiwari, Nhan Do
Filed: 10 Aug 22
Utility
Precision tuning of a page or word of non-volatile memory cells in an analog neural memory system
24 Oct 23
Numerous examples for performing tuning of a page or a word of non-volatile memory cells in an analog neural memory are disclosed.
Hieu Van Tran, Thuan Vu, Stephen Trinh, Stanley Hong, Anh Ly, Steven Lemke, Vipin Tiwari, Nhan Do
Filed: 4 Jul 22
Utility
Hierarchical ROM encoder system for performing address fault detection in a memory system
24 Oct 23
Various embodiments are disclosed for performing address fault detection in a memory system using a hierarchical ROM encoding system.
Xiaozhou Qian, Yaohua Zhu
Filed: 11 Feb 22
Utility
Split-gate flash memory cell with improved control gate capacitive coupling, and method of making same
24 Oct 23
A method of forming a memory device that includes forming a first insulation layer, a first conductive layer, and a second insulation layer on a semiconductor substrate, forming a trench in the second insulation layer to expose the upper surface of the first conductive layer, performing an oxidation process and a sloped etch process to reshape the upper surface to a concave shape, forming a third insulation layer on the reshaped upper surface, forming a conductive spacer on the third insulation layer, removing portions of the first conductive layer leaving a floating gate under the conductive spacer with the reshaped upper surface terminating at a side surface at a sharp edge, and forming a word line gate laterally adjacent to and insulated from the floating gate.
Leo Xing, Chunming Wang, Xian Liu, Nhan Do, Guo Xiang Song
Filed: 14 Jun 21
Utility
Method of Screening Non-volatile Memory Cells
19 Oct 23
A method for screening memory cells includes erasing the memory cells, weakly programming the memory cells to a modified erased state, performing a first read operation on the memory cells after the erasing and the weakly programming, screening any of the memory cells that exhibit a read current during the first read operation below a margin read current threshold M1, baking the memory cells after the first read operation, performing a second read operation on the memory cells after the baking, and screening any of the memory cells that exhibit a read current during the second read operation below the margin read current threshold M1.
Viktor Markov, ALEXANDER KOTOV
Filed: 6 Jul 22
Utility
Output circuitry for non-volatile memory array in neural network
17 Oct 23
A number of circuits for use in an output block coupled to a non-volatile memory array in a neural network are disclosed.
Farnood Merrikh Bayat, Xinjie Guo, Dmitri Strukov, Nhan Do, Hieu Van Tran, Vipin Tiwari, Mark Reiten
Filed: 22 Apr 21
Utility
Artificial Neural Network Comprising a Three-dimensional Integrated Circuit
12 Oct 23
Numerous examples are disclosed of an artificial neural network comprising a three-dimensional integrated circuit.
Hieu Van Tran, Mark Reiten, Nhan Do
Filed: 23 Jun 22
Utility
Artificial Neural Network Comprising Reference Array for I-v Slope Configuration
12 Oct 23
Numerous examples are disclosed of an artificial neural network comprising a plurality of reference arrays used for configuration of a vector-by-matrix multiplication array.
Hieu Van Tran, THUAN VU, STANLEY HONG, STEPHEN TRINH, STEVEN LEMKE, LOUISA SCHNEIDER, NHAN DO
Filed: 23 Jun 22
Utility
Vector-by-matrix-multiplication Array Utilizing Analog Inputs
12 Oct 23
Numerous examples are disclosed of an artificial neural network that comprises vector-by-matrix multiplication arrays utilizing analog inputs.
Hieu Van Tran, Thuan Vu, Stanley Hong, Stephen Trinh, Mark Reiten
Filed: 23 Jun 22
Utility
Vector-by-matrix-multiplication Array Utilizing Analog Outputs
12 Oct 23
Numerous examples are disclosed of an artificial neural network that comprises vector-by-matrix multiplication arrays utilizing analog outputs.
Hieu Van Tran, THUAN VU, STANLEY HONG, STEPHEN TRINH, MARK REITEN
Filed: 23 Jun 22
Utility
Compensation for leakage in an array of analog neural memory cells in an artificial neural network
10 Oct 23
In one example, a method is disclosed of compensating for leakage in an array of analog neural non-volatile memory cells, wherein the array is arranged in rows and columns, wherein each row is coupled to a word line and each column is coupled to a bitline, the method comprising measuring leakage for a column of analog neural non-volatile memory cells coupled to a bitline; storing the measured leakage value; and applying the measured leakage value during a read operation of the column of analog neural non-volatile memory cells to compensate for the leakage.
Hieu Van Tran, Thuan Vu, Stephen Trinh, Stanley Hong, Anh Ly, Steven Lemke, Nha Nguyen, Vipin Tiwari, Nhan Do
Filed: 13 Jun 22
Utility
Calibration of Electrical Parameters In a Deep Learning Artificial Neural Network
28 Sep 23
Numerous examples are disclosed for performing calibration of various electrical parameters in a deep learning artificial neural network.
Hieu Van Tran
Filed: 19 Apr 22
Utility
Method of reducing random telegraph noise in non-volatile memory by grouping and screening memory cells
26 Sep 23
A method of programing a memory device having a plurality of memory cell groups where each of the memory cell group includes N non-volatile memory cells, where N is an integer greater than or equal to 2.
Viktor Markov, Alexander Kotov
Filed: 22 Sep 21
Utility
Method of Forming a Device with Planar Split Gate Non-volatile Memory Cells, Planar HV Devices, and Finfet Logic Devices on a Substrate
14 Sep 23
A method of forming a device on a silicon substrate having first, second and third areas includes recessing an upper substrate surface in the first and third areas, forming an upwardly extending silicon fin in the second area, forming first source, drain and channel regions in the first area, forming second source, drain and channel regions in the fin, forming third source, drain and channel regions in the third area, forming a floating gate over a first portion of the first channel region using a first polysilicon deposition, forming an erase gate over the first source region and a device gate over the third channel region using a second polysilicon deposition, and forming a word line gate over a second portion of the first channel region, a control gate over the floating gate, and a logic gate over the second channel region using a metal deposition.
Serguei Jourba, Catherine Decobert, Feng Zhou, Jinho Kim, Xian Liu, Nhan Do
Filed: 25 May 22