540 patents
Utility
Power semiconductor device with reduced strain
9 Jan 24
Strategic placement and patterning of electrodes, vias, and metal runners can significantly reduce strain in a power semiconductor die.
Daniel Jenner Lichtenwalner, Edward Robert Van Brunt, Thomas E. Harrington, III, Shadi Sabri, Brett Hull, Brice McPherson, Joe W. McPherson
Filed: 17 Feb 21
Utility
Field effect transistors with modified access regions
9 Jan 24
A transistor device includes a semiconductor epitaxial layer structure including a channel layer and a barrier layer on the channel layer, wherein the barrier layer has a higher bandgap than the channel layer.
Kyoung-Keun Lee, Fabian Radulescu, Scott Sheppard
Filed: 20 May 21
Utility
Group III nitride-based radio frequency transistor amplifiers having source, gate and/or drain conductive vias
2 Jan 24
RF transistor amplifiers include a Group III nitride-based RF transistor amplifier die that includes a semiconductor layer structure, a conductive source via that is connected to a source region of the Group III nitride-based RF transistor amplifier die, the conductive source via extending through the semiconductor layer structure, and an additional conductive via that extends through the semiconductor layer structure.
Basim Noori, Marvin Marbell, Qianli Mu, Kwangmo Chris Lim, Michael E. Watts, Mario Bokatius, Jangheon Kim
Filed: 29 Mar 21
Utility
Group III-nitride high-electron mobility transistors with buried p-type layers and process for making the same
2 Jan 24
An apparatus includes a substrate.
Saptharishi Sriram, Thomas Smith, Alexander Suvorov, Christer Hallin
Filed: 16 Dec 20
Utility
Methods and Systems for Implementing a Modular Platform Implementing Active Devices
28 Dec 23
A modular platform includes a mother board and at least one daughter board.
Adam ANDERS, Julius RICE, Bart GARROTT
Filed: 24 Jun 22
Utility
Top Side Cooled Semiconductor Packages
28 Dec 23
Top-side cooled semiconductor packages are disclosed.
Adil Salman, Ajay Sekar Chandrasekaran, Kuldeep Saxena
Filed: 24 Jun 22
Utility
Modular Power Transistor Component Assemblies with Flip Chip Interconnections
28 Dec 23
A transistor device package includes a transistor die comprising a gate terminal, a drain terminal, and a source terminal, and a passive component assembly including the transistor die on a surface thereof and comprising one or more passive electrical components electrically coupled to the gate terminal, the drain terminal, and/or the source terminal.
Qianli Mu, Michael DeVita, Alexander Komposch, Basim Noori
Filed: 24 Jun 22
Utility
Silicon Carbide Based Integrated Passive Devices for Impedence Matching of Radio Frequency Power Devices and Process of Implementing the Same
28 Dec 23
An amplifier circuit that includes an RF amplifier; an impedance matching network; a higher order harmonic termination circuit; a fundamental frequency matching circuit; and an integrated passive device (IPD) that includes a silicon carbide (SiC) substrate.
Haedong JANG, Marvin MARBELL, Jeremy FISHER
Filed: 24 Jun 22
Utility
Semiconductor Devices Having On-chip Gate Resistors
28 Dec 23
Power semiconductor devices comprise a gate pad, a gate bus, and a gate resistor that is electrically interposed between the gate pad and the gate bus and comprises a wide band-gap semiconductor material region.
Rahul R. Potera, Prasanna Obala Bhuvanesh, Shadi Sabri, Roberto M. Schupbach, Jianwen Shao
Filed: 23 Jun 22
Utility
Wide Bandgap Transistors with Gate-source Field Plates
28 Dec 23
A transistor comprising an active region having a channel layer, with source and drain electrodes formed in contact with the active region and a gate formed between the source and drain electrodes and in contact with the active region.
Yifeng Wu, Primit Parikh, Umesh Mishra, Scott Sheppard
Filed: 11 Sep 23
Utility
Gate Trench Power Semiconductor Devices Having Improved Breakdown Performance and Methods of Forming Such Devices
28 Dec 23
A semiconductor device includes a semiconductor layer structure comprising a gate trench formed in an upper surface thereof, a gate finger in the gate trench, a supplemental dielectric layer on an upper surface of the gate finger and vertically overlaps the gate trench, and a gate connector on an upper surface of the supplemental dielectric layer and on an upper surface of the gate finger.
Madankumar Sampath, Woongsun Kim, Naeem Islam, Sei-Hyung Ryu
Filed: 23 Jun 22
Utility
Methods of Forming Ohmic Contacts on Semiconductor Devices with Trench/mesa Structures
28 Dec 23
A method of forming ohmic contacts on a semiconductor structure having a p-type region and an n-type region includes depositing a first metal on the n-type region, annealing the structure at a first contact anneal temperature to form a first ohmic contact on the n-type region, depositing a second metal on the first ohmic contact and on the p-type region, and annealing the structure at a second contact anneal temperature, less than the first contact anneal temperature, to form a second ohmic contact on the p-type region.
Madankumar Sampath, Sei-Hyung Ryu, Rahul R. Potera
Filed: 24 Jun 22
Utility
Methods of Forming Uniformly Doped Deep Implanted Regions In Silicon Carbide and Silicon Carbide Layers Including Uniformly Doped Implanted Regions
28 Dec 23
A method of forming a buried implanted region in a silicon carbide semiconductor layer includes implanting first dopant ions into the silicon carbide semiconductor layer at a first dose and first implant energy to form a first channelized doping profile having a first de-channeled peak at a first depth in the silicon carbide semiconductor layer and a first channeled peak at a second depth that is greater than the first depth.
Rahul R. Potera, Steven Rogers, Edward Robert Van Brunt
Filed: 24 Jun 22
Utility
Semiconductor Device with Selectively Grown Field Oxide Layer In Edge Termination Region
28 Dec 23
A semiconductor device includes a drift region, an active region in the drift region, and an edge termination region in the drift region adjacent to the active region.
In-Hwan Ji, Edward Robert Van Brunt, Woongsun Kim
Filed: 24 Jun 22
Utility
Radio Frequency Power Amplifier Implementing a Gain Equalizer and a Process of Implementing the Same
28 Dec 23
An amplifier includes an input impedance matching network; at least one transistor; and a gain equalizer configured to equalize gain.
Christophe JOLY
Filed: 23 Jun 22
Utility
Packages with Backside Mounted Die and Exposed Die Interconnects and Methods of Fabricating the Same
28 Dec 23
A method of fabricating a semiconductor device includes forming a protective structure on at least one die on a substrate.
Michael DeVita, Qianli Mu
Filed: 24 Jun 22
Utility
Semiconductor Device Packages with Exposed Heat Dissipating Surfaces and Methods of Fabricating the Same
28 Dec 23
A semiconductor device package includes an interconnect structure with a first surface having at least one die thereon and a second surface that is opposite the first surface and is configured to be coupled to an external device.
Alexander Komposch, Eng Wah Woo, Soon Lee Liew, Kok Meng Kam
Filed: 24 Jun 22
Utility
Optimization of Power Module Performance Via Parasitic Mutual Coupling
28 Dec 23
The present disclosure relates to a power module with a power path extending through a first field-effect transistor (FET) and a second FET.
Blake Whitmore Nelson, Brian DeBoi, Daniel John Martin
Filed: 26 Jun 22
Utility
Semiconductor Transistors Having Minimum Gate-to-source Voltage Clamp Circuits
28 Dec 23
Transistors are provided that comprise a silicon carbide based semiconductor layer structure, a first current terminal, a second current terminal, a gate terminal, and a minimum gate terminal-to-second current terminal voltage clamp circuit in the semiconductor layer structure that is coupled between the gate terminal and the second current terminal.
Rahul R. Potera, Andreas Scholze, Jianwen Shao, Edward R. Van Brunt, Philipp Steinmann, James T. Richmond
Filed: 13 Sep 23
Utility
Power Module
21 Dec 23
A power module has a substrate having a top side with a first device pad and a second device pad.
Brice McPherson
Filed: 20 Jun 22