540 patents
Page 2 of 27
Utility
Power Module
21 Dec 23
A power module has a substrate having a top side with a first device pad and a second device pad.
Brice McPherson
Filed: 20 Jun 22
Utility
Power Package Having Connected Components and Processes Implementing the Same
14 Dec 23
A semiconductor package includes a metal submount; at least one transistor die arranged on said metal submount; and one or more metal contacts configured to be located adjacent said metal submount by a connection.
Alexander KOMPOSCH, Liew Soon LEE, Eng Wah WOO
Filed: 10 Jun 22
Utility
Device and process for fault detection of a power device
12 Dec 23
A power device fault detection circuit includes a first fault detector configured to measure an output signal of at least one power device and output a first fault signal when a voltage of the output signal of the at least one power device exceeds a first voltage reference level after a first time period; and a second fault detector configured to measure an output signal of the at least one power device and output a second fault signal when a voltage of the output signal of the at least one power device exceeds a second voltage reference level after a second time period, where the first time period implemented by the first fault detector is shorter than the second time period implemented by the second fault detector.
Adam E. Anders
Filed: 8 Jun 21
Utility
Methods for pillar connection on frontside and passive device integration on backside of die
12 Dec 23
An integrated circuit device includes a radio frequency transistor amplifier die having a first surface, a second surface, a semiconductor layer structure that is between the first and second surfaces and includes a plurality of transistor cells adjacent the first surface, and terminals coupled to the transistor cells.
Terry Alcorn, Daniel Namishia, Fabian Radulescu
Filed: 21 Mar 22
Utility
Encapsulation stack for improved humidity performance and related fabrication methods
12 Dec 23
A transistor device includes a substrate, a semiconductor structure on the substrate, a metallization layer comprising a non-planar surface on a surface of the semiconductor structure, a non-planar encapsulation layer on the non-planar surface of the metallization layer, the non-planar encapsulation layer comprising a non-planar encapsulant surface that is opposite the non-planar surface, and a self-planarizing encapsulation layer on the non-planar encapsulation layer and comprising a planarized surface that is opposite the non-planar encapsulant surface.
Chris Hardiman, Daniel Namishia, Kyle Bothe, Elizabeth Keenan
Filed: 30 Jul 21
Utility
Power silicon carbide based semiconductor devices with improved short circuit capabilities and methods of making such devices
12 Dec 23
A power semiconductor device has a semiconductor layer structure that includes a silicon carbide drift region having a first conductivity type, first and second wells in the silicon carbide drift region that are doped with dopants having a second conductivity type, and a JFET region between the first and second wells.
Kijeong Han, Joohyung Kim, Sei-Hyung Ryu
Filed: 27 Aug 20
Utility
Plasma-based Barrier Layer Removal Method for Increasing Peak Transconductance While Maintaining On-state Resistance and Related Devices
7 Dec 23
A transistor device includes a semiconductor structure comprising a channel layer and a barrier layer; source and drain contacts on the semiconductor structure; and a gate on the semiconductor structure between the source and drain contacts.
Chris Hardiman, Kyoung-Keun Lee, Kyle Bothe, Fabian Radulescu
Filed: 7 Jun 22
Utility
Method for Reducing Parasitic Capacitance and Increasing Peak Transconductance While Maintaining On-state Resistance and Related Devices
7 Dec 23
A transistor device includes a semiconductor structure comprising a channel layer and a barrier layer, source and drain contacts on the semiconductor structure, and a conductive element in a recess in the barrier layer between the source and drain contacts.
Chris Hardiman, Matthew King, Kyle Bothe
Filed: 2 May 23
Utility
Packaging for RF transistor amplifiers
5 Dec 23
RF transistor amplifiers an RF transistor amplifier die having a semiconductor layer structure, an interconnect structure having first and second opposing sides, wherein the first side of the interconnect structure is adjacent a surface of the RF transistor amplifier die such that the interconnect structure and the RF transistor amplifier die are in a stacked arrangement, and one or more circuit elements on the first and/or second side of the interconnect structure.
Basim Noori, Marvin Marbell, Scott Sheppard, Kwangmo Chris Lim, Alexander Komposch, Qianli Mu
Filed: 11 Sep 20
Utility
Power semiconductor devices having gate trenches and buried edge terminations and related methods
5 Dec 23
Semiconductor devices include a semiconductor layer structure comprising a drift region that includes a wide band-gap semiconductor material.
Daniel J. Lichtenwalner, Edward R. Van Brunt, Brett Hull
Filed: 19 Nov 20
Utility
Group III nitride-based radio frequency amplifiers having back side source, gate and/or drain terminals
5 Dec 23
RF amplifiers are provided that include an interconnection structure and a Group III nitride-based RF amplifier die that is mounted on top of the interconnection structure.
Michael E. Watts, Mario Bokatius, Jangheon Kim, Basim Noori, Qianli Mu, Kwangmo Chris Lim, Marvin Marbell
Filed: 24 Mar 21
Utility
Gate trench power semiconductor devices having improved deep shield connection patterns
5 Dec 23
A power semiconductor device comprises a semiconductor layer structure having a wide band-gap drift region having a first conductivity type, a gate trench having first and second opposed sidewalls that extend in a first direction in an upper portion of the semiconductor layer structure, first and second well regions having a second conductivity type in the upper portion of the semiconductor layer structure, the first well region comprising part of the first sidewall and the second well region comprising part of the second sidewall.
Naeem Islam, Woongsun Kim, Daniel J. Lichtenwalner, Sei-Hyung Ryu
Filed: 15 Feb 23
Utility
Laser-assisted method for parting crystalline material
28 Nov 23
A method for processing a crystalline substrate to form multiple patterns of subsurface laser damage facilitates subsequent fracture of the substrate to yield first and second substrate portions of reduced thickness.
Matthew Donofrio, John Edmond, Harshad Golakia
Filed: 23 Jun 20
Utility
Packaged transistor having die attach materials with channels and process of implementing the same
28 Nov 23
A package includes a circuit that includes at least one active area and at least one secondary device area, a support configured to support the circuit, and a die attach material.
Mitch Flowers, Erwin Cohen, Alexander Komposch, Larry Christopher Wall
Filed: 30 Oct 20
Utility
Power Semiconductor Devices Having Moisture Barriers
23 Nov 23
A power semiconductor device comprises a package, a power semiconductor die within the package, and a moisture barrier on an upper surface and side surfaces of an exterior of the package.
Dev Balaraman, Geza Dezsi, Daniel Richter
Filed: 18 May 22
Utility
Vertical Power Devices Having Mesas and Etched Trenches Therebetween
16 Nov 23
A vertical semiconductor and method for fabricating the same is disclosed.
Daniel Jenner Lichtenwalner, Sei-Hyung Ryu
Filed: 13 May 22
Utility
Gate Trench Power Semiconductor Devices Having Improved Deep Shield Connection Patterns
16 Nov 23
A power semiconductor device includes a semiconductor layer structure comprising a drift region of a first conductivity type and a well region of a second conductivity type, a plurality of gate trenches including respective gate insulating layers and gate electrodes therein extending into the drift region, respective shielding patterns of the second conductivity type in respective portions of the drift region adjacent the gate trenches, and respective conduction enhancing regions of the first conductivity type in the respective portions of the drift region.
Woongsun Kim, Sei-Hyung Ryu, Daniel Jenner Lichtenwalner, Naeem Islam
Filed: 20 Jul 23
Utility
Group III Nitride-based Monolithic Microwave Integrated Circuits Including Static Random Access Memory Blocks with Associated Addressing and Buffering Circuits
9 Nov 23
A monolithic microwave integrated circuit comprises a monolithic substrate, a Group III nitride-based channel layer on the monolithic substrate, a Group III nitride-based barrier layer on the monolithic substrate, a Group III nitride-based channel layer in between the monolithic substrate and the Group III nitride-based barrier layer, a radio frequency circuit that includes a plurality of depletion mode RF transistors that are formed in the Group III nitride-based channel and barrier layers, and a static random access memory (“SRAM”) circuit that includes a SRAM block having a plurality of SRAM cells arranged in rows and columns, the SRAM circuit including a plurality of depletion mode transistors and a plurality of enhancement mode transistors that are formed in the Group III nitride-based channel and barrier layers.
Jeremy Fisher
Filed: 5 May 22
Utility
Dynamic Performance of On-chip Current Sensors
9 Nov 23
A semiconductor device includes a device region and an on-chip sensor region, such as an on-chip current sensor region.
Madankumar Sampath, Sei-Hyung Ryu, Edward Robert Van Brunt
Filed: 4 May 22
Utility
Dual Inline Power Module
9 Nov 23
A power module is provided with a substrate, power devices, and a housing.
Brice McPherson, Shashwat Singh, Roberto M. Schupbach
Filed: 4 May 22